Unified Coverage Report :: Module :: otp_ctrl

Module : otp_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.75	95.10	88.12	77.52		96.00	97.01

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	90.86	95.10	88.12	78.08		96.00	97.01

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.86	95.10	88.12	78.08		96.00	97.01

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.69	91.60	89.36	85.02	79.05	91.53	95.59

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
core_tlul_assert_device	100.00	100.00				100.00	100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_alert_tx[2].u_prim_alert_sender	100.00			100.00
gen_alert_tx[3].u_prim_alert_sender	100.00			100.00
gen_alert_tx[4].u_prim_alert_sender	77.78			77.78
gen_bufs[0].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[0].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[1].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[1].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[2].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[2].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[3].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[3].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[4].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[4].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[5].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[5].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[6].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[6].u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_bufs[7].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[7].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_partitions[0].gen_unbuffered.u_part_unbuf	81.38	91.85	93.55	74.47	48.00	85.96	94.44
gen_partitions[1].gen_unbuffered.u_part_unbuf	92.14	97.04	96.77	96.81	72.00	92.98	97.22
gen_partitions[2].gen_unbuffered.u_part_unbuf	89.17	94.07	96.77	95.74	60.00	91.23	97.22
gen_partitions[3].gen_buffered.u_part_buf	82.43	83.01	76.09	93.78	79.31	78.31	84.09
gen_partitions[4].gen_buffered.u_part_buf	87.65	92.06	76.92	94.30	86.11	85.23	91.30
gen_partitions[5].gen_buffered.u_part_buf	87.56	92.06	76.92	93.73	86.11	85.23	91.30
gen_partitions[6].gen_buffered.u_part_buf	88.28	92.06	76.92	93.73	86.11	85.23	95.65
gen_partitions[7].gen_lifecycle.u_part_buf	77.88	69.82	70.83	71.85	95.24	73.85	85.71
otp_ctrl_core_csr_assert	84.62						84.62
prim_tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_arb	87.10	92.31	62.75			100.00	93.33
u_edn_req	92.19	100.00	93.75			100.00	75.00
u_intr_error	100.00	100.00	100.00			100.00	100.00
u_intr_operation_done	100.00	100.00	100.00			100.00	100.00
u_keygmr_key_valid	100.00	100.00				100.00
u_otp	96.18	91.73	94.82	100.00	100.00	90.52	100.00
u_otp_arb	93.61	93.01	87.68			100.00	93.75
u_otp_ctrl_dai	87.30	89.34	90.71	100.00	73.68	85.95	84.09
u_otp_ctrl_kdi	95.35	99.26	94.43	100.00	86.36	94.68	97.37
u_otp_ctrl_lci	95.12	95.08	83.33	100.00	100.00	92.31	100.00
u_otp_ctrl_lfsr_timer	90.46	98.18	78.75	76.92	100.00	88.89	100.00
u_otp_ctrl_scrmbl	93.29	81.50	100.00	100.00	80.00	98.21	100.00
u_otp_init_sync	100.00	100.00				100.00
u_otp_rsp_fifo	94.70	100.00	78.79			100.00	100.00
u_part_sel_idx	82.27	76.81	98.44			100.00	53.85
u_prim_lc_sender_otp_broadcast_valid	100.00	100.00				100.00
u_prim_lc_sender_rma_token_valid	100.00	100.00				100.00
u_prim_lc_sender_secrets_valid	100.00	100.00				100.00
u_prim_lc_sender_test_tokens_valid	100.00	100.00				100.00
u_prim_lc_sync_check_byp_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_creator_seed_sw_rw_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_escalate_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_seed_hw_rd_en	100.00	100.00				100.00	100.00
u_reg_core	99.15	99.60	96.17	100.00		100.00	100.00
u_scrmbl_mtx	76.20	83.33	77.70			100.00	43.75
u_tlul_adapter_sram	91.72	89.54	84.55			92.77	100.00
u_tlul_lc_gate	86.31	95.45	100.00		57.14	91.43	87.50

Line Coverage for Module : otp_ctrl

	Line No.	Total	Covered	Percent
TOTAL		143	136	95.10
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
ALWAYS	264	14	13	92.86
ALWAYS	288	3	3	100.00
ALWAYS	304	7	7	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	362	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
ALWAYS	375	3	3	100.00
ALWAYS	399	19	19	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
ALWAYS	464	9	9	100.00
ALWAYS	486	10	10	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	607	1	1	100.00
CONT_ASSIGN	730	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
ALWAYS	841	2	2	100.00
ALWAYS	899	2	2	100.00
ALWAYS	926	4	4	100.00
CONT_ASSIGN	953	1	1	100.00
ALWAYS	956	3	3	100.00
CONT_ASSIGN	1008	1	1	100.00
CONT_ASSIGN	1010	1	1	100.00
CONT_ASSIGN	1044	1	1	100.00
CONT_ASSIGN	1095	1	0	0.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1265	1	0	0.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1301	1	1	100.00
ALWAYS	1313	2	2	100.00
CONT_ASSIGN	1327	1	1	100.00
ALWAYS	1355	9	9	100.00
CONT_ASSIGN	1386	1	1	100.00
CONT_ASSIGN	1387	1	1	100.00
CONT_ASSIGN	1389	1	1	100.00
CONT_ASSIGN	1391	1	1	100.00
CONT_ASSIGN	1395	1	1	100.00
CONT_ASSIGN	1397	1	1	100.00
CONT_ASSIGN	1399	1	1	100.00
CONT_ASSIGN	1404	1	1	100.00
CONT_ASSIGN	1406	1	1	100.00
CONT_ASSIGN	1408	1	1	100.00
CONT_ASSIGN	1440	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1446	1	1	100.00
CONT_ASSIGN	1450	1	1	100.00
CONT_ASSIGN	1454	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
234	8	8
264	1	1
265	1	1
266	1	1
267	1	1
268	1	1
269	1	1
272	0	1
			MISSING_ELSE
277	1	1
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
288	1	1
289	1	1
291	1	1
304	1	1
309	1	1
310	1	1
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
354	1	1
358	1	1
362	1	1
363	1	1
371	1	1
372	1	1
375	1	1
376	1	1
378	1	1
399	1	1
400	1	1
401	1	1
403	1	1
405	1	1
408	1	1
410	1	1
413	1	1
414	1	1
			MISSING_ELSE
418	1	1
420	1	1
424	1	1
427	1	1
429	1	1
434	1	1
435	1	1
			MISSING_ELSE
437	1	1
438	1	1
			MISSING_ELSE
443	1	1
453	1	1
461	1	1
464	1	1
465	1	1
466	1	1
467	1	1
468	1	1
470	1	1
471	1	1
472	1	1
473	1	1
486	1	1
488	1	1
490	1	1
492	1	1
494	1	1
503	1	1
505	1	1
506	1	1
507	1	1
508	1	1
550	1	1
558	1	1
605	1	1
607	1	1
730	1	1
731	1	1
732	1	1
762	1	1
764	1	1
841	1	1
842	1	1
899	1	1
900	1	1
926	1	1
927	1	1
928	1	1
929	1	1
953	1	1
956	1	1
957	1	1
959	1	1
1008	1	1
1010	1	1
1044	1	1
1095	0	1
1150	3	3
1205	0	4
1265	0	1
1277	1	1
1301	1	1
1313	1	1
1314	1	1
1327	1	1
1355	1	1
1356	1	1
1357	1	1
1358	1	1
1360	1	1
1361	1	1
1362	1	1
1363	1	1
1364	1	1
1386	1	1
1387	1	1
1389	1	1
1391	1	1
1395	1	1
1397	1	1
1399	1	1
1404	1	1
1406	1	1
1408	1	1
1440	1	1
1442	1	1
1446	1	1
1450	1	1
1454	1	1

---

Cond Coverage for Module : otp_ctrl

	Total	Covered	Percent
Conditions	101	89	88.12
Logical	101	89	88.12
Non-Logical	0	0
Event	0	0

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b0) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[0].PartEnd))
             --------------1-------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b01101100000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10
1	1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11010000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10
1	1	Covered	T10

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10
1	1	Covered	T10

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10
1	1	Covered	T10

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10
1	1	Covered	T10

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10

 LINE       268
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       277
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       278
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       354
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       371
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       401
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Not Covered

 LINE       410
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       414
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T19,T20

 LINE       434
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T3,T19,T20

 LINE       443
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T2,T3,T17
0	0	1	0	Covered	T14,T15,T16
0	1	0	0	Covered	T14,T15,T16
1	0	0	0	Covered	T49

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T202
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T202

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T202
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T202

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T202
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T202

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T202
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T202

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T202
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T202

 LINE       605
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T4,T8

 LINE       607
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T4

 LINE       730
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       731
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       732
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       842
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1386
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T29

 LINE       1404
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T18

 LINE       1404
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T18

 LINE       1406
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T29

 LINE       1406
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T29

 LINE       1408
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T29

 LINE       1408
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T29

---

Toggle Coverage for Module : otp_ctrl

	Total	Covered	Percent
Totals	155	136	87.74
Total Bits	10960	8496	77.52
Total Bits 0->1	5480	4249	77.54
Total Bits 1->0	5480	4247	77.50

Ports	155	136	87.74
Port Bits	10960	8496	77.52
Port Bits 0->1	5480	4249	77.54
Port Bits 1->0	5480	4247	77.50

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_o.edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i.edn_fips	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i.edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
core_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T19	Yes	T1,T3,T19	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_error	Yes	Yes	T1,T9,T8	Yes	T1,T9,T8	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T9,T18	Yes	T1,T9,T18	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T18,T4	Yes	T3,T18,T4	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T1,T9,T4	Yes	T1,T9,T18	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T3,T18,T4	Yes	T3,T18,T4	INPUT
prim_tl_i.a_address[31:0]	Yes	Yes	T3,T4,T204	Yes	T3,T18,T4	INPUT
prim_tl_i.a_source[7:0]	Yes	Yes	T1,T18,T4	Yes	T1,T3,T18	INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T3,T4,T204	Yes	T3,T18,T4	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T1,T9,T18	Yes	T1,T9,T18	INPUT
prim_tl_i.a_valid	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
prim_tl_o.a_ready	Yes	Yes	T1,T11,T7	Yes	T1,T11,T7	OUTPUT
prim_tl_o.d_error	Yes	Yes	T11,T12,T13	Yes	T13,T10,T89	OUTPUT
prim_tl_o.d_user.data_intg[6:0]	Yes	Yes	T13,T206,T90	Yes	T13,T206,T90	OUTPUT
prim_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T9,*T4	Yes	T1,T9,T4	OUTPUT
prim_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T11,T12,T13	Yes	T13,T10,T206	OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	Yes	Yes	T1,T9,T5	Yes	T1,T9,T5	OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T10,T206,T89	Yes	T10,T206,T89	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T1,*T9,*T4	Yes	T1,T9,T4	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT
intr_otp_operation_done_o	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	OUTPUT
intr_otp_error_o	Yes	Yes	T2,T17,T46	Yes	T2,T17,T46	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T19,T20	Yes	T3,T19,T20	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T11,T12,T202	Yes	T11,T12,T202	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T11,T12,T202	Yes	T11,T12,T202	INPUT
alert_rx_i[3].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T11,T12,T202	Yes	T11,T12,T202	INPUT
alert_rx_i[4].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T19,T20	Yes	T3,T19,T20	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T11,T12,T202	Yes	T11,T12,T202	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T11,T12,T202	Yes	T11,T12,T202	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T11,T12,T202	Yes	T11,T12,T202	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0]	No	No		No		OUTPUT
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0]	Yes	Yes	T4,T20,T33	Yes	T18,T5,T46	INPUT
pwr_otp_i.otp_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_otp_o.otp_idle	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_otp_o.otp_done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_otp_vendor_test_i.ctrl[31:0]	No	No		No		INPUT
lc_otp_vendor_test_o.status[31:0]	No	No		No		OUTPUT
lc_otp_program_i.count[16:0]	No	No		No		INPUT
lc_otp_program_i.count[17]	Yes	Yes	*T207,*T208,*T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[18]	No	No		No		INPUT
lc_otp_program_i.count[19]	Yes	Yes	*T207,*T208,*T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[21:20]	No	No		No		INPUT
lc_otp_program_i.count[22]	Yes	Yes	*T207,*T208,*T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[26:23]	No	No		No		INPUT
lc_otp_program_i.count[27]	Yes	Yes	*T207,*T208,*T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[33:28]	No	No		No		INPUT
lc_otp_program_i.count[35:34]	Yes	Yes	T207,T208,T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[36]	No	No		No		INPUT
lc_otp_program_i.count[37]	Yes	Yes	*T207,*T208,*T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[40:38]	No	No		No		INPUT
lc_otp_program_i.count[41]	Yes	Yes	*T207,*T208,*T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[42]	No	No		No		INPUT
lc_otp_program_i.count[43]	Yes	Yes	*T207,*T208,*T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[45:44]	No	No		No		INPUT
lc_otp_program_i.count[46]	Yes	Yes	*T207,*T208,*T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[48:47]	No	No		No		INPUT
lc_otp_program_i.count[49]	Yes	Yes	*T207,*T211,*T212	Yes	T29,T207,T213	INPUT
lc_otp_program_i.count[52:50]	No	No		No		INPUT
lc_otp_program_i.count[53]	Yes	Yes	*T207,*T211,*T212	Yes	T29,T207,T213	INPUT
lc_otp_program_i.count[55:54]	No	No		No		INPUT
lc_otp_program_i.count[56]	Yes	Yes	*T207,*T211,*T212	Yes	T29,T207,T213	INPUT
lc_otp_program_i.count[59:57]	No	No		No		INPUT
lc_otp_program_i.count[60]	Yes	Yes	*T207,*T211,*T212	Yes	T29,T207,T213	INPUT
lc_otp_program_i.count[65:61]	No	No		No		INPUT
lc_otp_program_i.count[66]	Yes	Yes	*T207,*T211,*T212	Yes	T29,T207,T213	INPUT
lc_otp_program_i.count[72:67]	No	No		No		INPUT
lc_otp_program_i.count[76:73]	Yes	Yes	T207,T211,T212	Yes	T29,T207,T213	INPUT
lc_otp_program_i.count[80:77]	No	No		No		INPUT
lc_otp_program_i.count[81]	Yes	Yes	*T207,*T210,*T212	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[82]	No	No		No		INPUT
lc_otp_program_i.count[84:83]	Yes	Yes	T207,T210,T212	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[87:85]	No	No		No		INPUT
lc_otp_program_i.count[88]	Yes	Yes	*T207,*T210,*T212	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[91:89]	No	No		No		INPUT
lc_otp_program_i.count[92]	Yes	Yes	*T207,*T210,*T212	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[93]	No	No		No		INPUT
lc_otp_program_i.count[94]	Yes	Yes	*T207,*T210,*T212	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[95]	No	No		No		INPUT
lc_otp_program_i.count[97:96]	Yes	Yes	T207,T210,T212	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[99:98]	No	No		No		INPUT
lc_otp_program_i.count[100]	Yes	Yes	*T207,*T210,*T212	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[108:101]	No	No		No		INPUT
lc_otp_program_i.count[110:109]	Yes	Yes	T207,T210,T212	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[116:111]	No	No		No		INPUT
lc_otp_program_i.count[118:117]	Yes	Yes	T6,T207,T214	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[122:119]	No	No		No		INPUT
lc_otp_program_i.count[123]	Yes	Yes	*T6,*T207,*T214	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[126:124]	No	No		No		INPUT
lc_otp_program_i.count[132:127]	Yes	Yes	T6,*T207,T214	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[136:133]	No	No		No		INPUT
lc_otp_program_i.count[137]	Yes	Yes	*T6,*T214,*T210	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[145:138]	No	No		No		INPUT
lc_otp_program_i.count[147:146]	Yes	Yes	T6,T214,T215	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[157:148]	No	No		No		INPUT
lc_otp_program_i.count[158]	Yes	Yes	*T6,*T214,*T215	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[160:159]	No	No		No		INPUT
lc_otp_program_i.count[162:161]	Yes	Yes	T6,T214,T215	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[163]	No	No		No		INPUT
lc_otp_program_i.count[164]	Yes	Yes	*T6,*T214,*T215	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[166:165]	No	No		No		INPUT
lc_otp_program_i.count[167]	Yes	Yes	*T6,*T214,*T215	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[168]	No	No		No		INPUT
lc_otp_program_i.count[169]	Yes	Yes	*T6,*T214,*T215	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[179:170]	No	No		No		INPUT
lc_otp_program_i.count[180]	Yes	Yes	*T6,*T71,*T214	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[182:181]	No	No		No		INPUT
lc_otp_program_i.count[184:183]	Yes	Yes	T6,T71,T214	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[189:185]	No	No		No		INPUT
lc_otp_program_i.count[190]	Yes	Yes	*T6,*T71,*T214	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[192:191]	No	No		No		INPUT
lc_otp_program_i.count[193]	Yes	Yes	*T6,*T71,*T214	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[195:194]	No	No		No		INPUT
lc_otp_program_i.count[196]	Yes	Yes	*T6,*T71,*T214	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[199:197]	No	No		No		INPUT
lc_otp_program_i.count[202:200]	Yes	Yes	T6,T71,T214	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[213:203]	No	No		No		INPUT
lc_otp_program_i.count[214]	Yes	Yes	*T6,*T71,*T72	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[220:215]	No	No		No		INPUT
lc_otp_program_i.count[222:221]	Yes	Yes	T6,T71,T72	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[223]	No	No		No		INPUT
lc_otp_program_i.count[224]	Yes	Yes	*T6,*T71,*T72	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[231:225]	No	No		No		INPUT
lc_otp_program_i.count[232]	Yes	Yes	*T6,*T71,*T72	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[234:233]	No	No		No		INPUT
lc_otp_program_i.count[235]	Yes	Yes	*T6,*T71,*T72	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[236]	No	No		No		INPUT
lc_otp_program_i.count[237]	Yes	Yes	*T6,*T71,*T72	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[245:238]	No	No		No		INPUT
lc_otp_program_i.count[246]	Yes	Yes	*T6,*T72,*T214	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[247]	No	No		No		INPUT
lc_otp_program_i.count[248]	Yes	Yes	*T6,*T72,*T214	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[249]	No	No		No		INPUT
lc_otp_program_i.count[251:250]	Yes	Yes	T6,T72,T214	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[255:252]	No	No		No		INPUT
lc_otp_program_i.count[257:256]	Yes	Yes	T6,T71,T72	Yes	T7,T70,T71	INPUT
lc_otp_program_i.count[259:258]	No	No		No		INPUT
lc_otp_program_i.count[260]	Yes	Yes	*T6,*T71,*T72	Yes	T7,T70,T71	INPUT
lc_otp_program_i.count[261]	No	No		No		INPUT
lc_otp_program_i.count[263:262]	Yes	Yes	T6,T71,T72	Yes	T7,T70,T71	INPUT
lc_otp_program_i.count[273:264]	No	No		No		INPUT
lc_otp_program_i.count[274]	Yes	Yes	*T6,*T72,*T215	Yes	T29,T100,T216	INPUT
lc_otp_program_i.count[278:275]	No	No		No		INPUT
lc_otp_program_i.count[280:279]	Yes	Yes	T6,T72,T215	Yes	T29,T100,T216	INPUT
lc_otp_program_i.count[286:281]	No	No		No		INPUT
lc_otp_program_i.count[287]	Yes	Yes	*T6,*T72,*T215	Yes	T29,T100,T216	INPUT
lc_otp_program_i.count[289:288]	No	No		No		INPUT
lc_otp_program_i.count[290]	Yes	Yes	*T6,*T72,*T210	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[293:291]	No	No		No		INPUT
lc_otp_program_i.count[294]	Yes	Yes	*T6,*T72,*T210	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[296:295]	No	No		No		INPUT
lc_otp_program_i.count[297]	Yes	Yes	*T6,*T72,*T210	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[299:298]	No	No		No		INPUT
lc_otp_program_i.count[300]	Yes	Yes	*T6,*T72,*T210	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[304:301]	No	No		No		INPUT
lc_otp_program_i.count[305]	Yes	Yes	*T6,*T72,*T210	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[307:306]	No	No		No		INPUT
lc_otp_program_i.count[309:308]	Yes	Yes	T6,T72,T210	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[315:310]	No	No		No		INPUT
lc_otp_program_i.count[316]	Yes	Yes	*T6,*T72,*T210	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[318:317]	No	No		No		INPUT
lc_otp_program_i.count[319]	Yes	Yes	*T6,*T72,*T210	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[339:320]	No	No		No		INPUT
lc_otp_program_i.count[341:340]	Yes	Yes	T212,T217	Yes	T218,T208,T219	INPUT
lc_otp_program_i.count[348:342]	No	No		No		INPUT
lc_otp_program_i.count[349]	Yes	Yes	*T212,*T217	Yes	T218,T208,T219	INPUT
lc_otp_program_i.count[350]	No	No		No		INPUT
lc_otp_program_i.count[353:351]	Yes	Yes	T212,T217,*T220	Yes	T218,T208,T219	INPUT
lc_otp_program_i.count[354]	No	No		No		INPUT
lc_otp_program_i.count[356:355]	Yes	Yes	T220,T212,T221	Yes	T29,T100,T222	INPUT
lc_otp_program_i.count[358:357]	No	No		No		INPUT
lc_otp_program_i.count[359]	Yes	Yes	*T220,*T212,*T221	Yes	T29,T100,T222	INPUT
lc_otp_program_i.count[368:360]	No	No		No		INPUT
lc_otp_program_i.count[369]	Yes	Yes	*T220,*T212,*T221	Yes	T29,T70,T72	INPUT
lc_otp_program_i.count[370]	No	No		No		INPUT
lc_otp_program_i.count[371]	Yes	Yes	*T220,*T212,*T221	Yes	T29,T70,T72	INPUT
lc_otp_program_i.count[372]	No	No		No		INPUT
lc_otp_program_i.count[374:373]	Yes	Yes	T220,T212,T221	Yes	T29,T70,T72	INPUT
lc_otp_program_i.count[383:375]	No	No		No		INPUT
lc_otp_program_i.state[4:0]	No	No		No		INPUT
lc_otp_program_i.state[5]	Yes	Yes	*T220,*T212,*T221	Yes	T29,T70,T72	INPUT
lc_otp_program_i.state[7:6]	No	No		No		INPUT
lc_otp_program_i.state[8]	Yes	Yes	*T220,*T212,*T221	Yes	T29,T70,T72	INPUT
lc_otp_program_i.state[10:9]	No	No		No		INPUT
lc_otp_program_i.state[12:11]	Yes	Yes	T220,T212,T221	Yes	T29,T70,T72	INPUT
lc_otp_program_i.state[22:13]	No	No		No		INPUT
lc_otp_program_i.state[24:23]	Yes	Yes	T71,T220,T210	Yes	T29,T72,T100	INPUT
lc_otp_program_i.state[28:25]	No	No		No		INPUT
lc_otp_program_i.state[30:29]	Yes	Yes	T71,T220,T210	Yes	T29,T72,T100	INPUT
lc_otp_program_i.state[37:31]	No	No		No		INPUT
lc_otp_program_i.state[38]	Yes	Yes	*T71,*T214,*T220	Yes	T6,T29,T72	INPUT
lc_otp_program_i.state[43:39]	No	No		No		INPUT
lc_otp_program_i.state[44]	Yes	Yes	*T71,*T214,*T220	Yes	T6,T29,T72	INPUT
lc_otp_program_i.state[45]	No	No		No		INPUT
lc_otp_program_i.state[46]	Yes	Yes	*T71,*T214,*T220	Yes	T6,T29,T72	INPUT
lc_otp_program_i.state[54:47]	No	No		No		INPUT
lc_otp_program_i.state[55]	Yes	Yes	*T71,*T214,*T220	Yes	T6,T29,T72	INPUT
lc_otp_program_i.state[62:56]	No	No		No		INPUT
lc_otp_program_i.state[63]	Yes	Yes	*T71,*T214,*T220	Yes	T6,T29,T72	INPUT
lc_otp_program_i.state[71:64]	No	No		No		INPUT
lc_otp_program_i.state[72]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[74:73]	No	No		No		INPUT
lc_otp_program_i.state[75]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[76]	No	No		No		INPUT
lc_otp_program_i.state[77]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[78]	No	No		No		INPUT
lc_otp_program_i.state[79]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[82:80]	No	No		No		INPUT
lc_otp_program_i.state[83]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[88:84]	No	No		No		INPUT
lc_otp_program_i.state[91:89]	Yes	Yes	T71,T214,T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[94:92]	No	No		No		INPUT
lc_otp_program_i.state[95]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[97:96]	No	No		No		INPUT
lc_otp_program_i.state[98]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[100:99]	No	No		No		INPUT
lc_otp_program_i.state[101]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[102]	No	No		No		INPUT
lc_otp_program_i.state[103]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[107:104]	No	No		No		INPUT
lc_otp_program_i.state[109:108]	Yes	Yes	T71,T214,T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[112:110]	No	No		No		INPUT
lc_otp_program_i.state[113]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[124:114]	No	No		No		INPUT
lc_otp_program_i.state[125]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[128:126]	No	No		No		INPUT
lc_otp_program_i.state[131:129]	Yes	Yes	T71,T214,T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[137:132]	No	No		No		INPUT
lc_otp_program_i.state[138]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[139]	No	No		No		INPUT
lc_otp_program_i.state[141:140]	Yes	Yes	T71,T214,T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[144:142]	No	No		No		INPUT
lc_otp_program_i.state[145]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[148:146]	No	No		No		INPUT
lc_otp_program_i.state[149]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[150]	No	No		No		INPUT
lc_otp_program_i.state[151]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[154:152]	No	No		No		INPUT
lc_otp_program_i.state[156:155]	Yes	Yes	T71,T214,T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[159:157]	No	No		No		INPUT
lc_otp_program_i.state[160]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[162:161]	No	No		No		INPUT
lc_otp_program_i.state[163]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[166:164]	No	No		No		INPUT
lc_otp_program_i.state[167]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[168]	No	No		No		INPUT
lc_otp_program_i.state[169]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[172:170]	No	No		No		INPUT
lc_otp_program_i.state[173]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[174]	No	No		No		INPUT
lc_otp_program_i.state[175]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[176]	No	No		No		INPUT
lc_otp_program_i.state[177]	Yes	Yes	*T71,*T207,*T214	Yes	T29,T104,T207	INPUT
lc_otp_program_i.state[179:178]	No	No		No		INPUT
lc_otp_program_i.state[180]	Yes	Yes	*T71,*T207,*T214	Yes	T29,T104,T207	INPUT
lc_otp_program_i.state[185:181]	No	No		No		INPUT
lc_otp_program_i.state[186]	Yes	Yes	*T71,*T207,*T214	Yes	T29,T104,T207	INPUT
lc_otp_program_i.state[188:187]	No	No		No		INPUT
lc_otp_program_i.state[189]	Yes	Yes	*T71,*T207,*T214	Yes	T29,T104,T207	INPUT
lc_otp_program_i.state[192:190]	No	No		No		INPUT
lc_otp_program_i.state[193]	Yes	Yes	*T71,*T207,*T214	Yes	T29,T207,T223	INPUT
lc_otp_program_i.state[195:194]	No	No		No		INPUT
lc_otp_program_i.state[196]	Yes	Yes	*T71,*T207,*T214	Yes	T29,T207,T223	INPUT
lc_otp_program_i.state[201:197]	No	No		No		INPUT
lc_otp_program_i.state[203:202]	Yes	Yes	T71,T207,T214	Yes	T29,T207,T223	INPUT
lc_otp_program_i.state[204]	No	No		No		INPUT
lc_otp_program_i.state[205]	Yes	Yes	*T71,*T207,*T214	Yes	T29,T207,T223	INPUT
lc_otp_program_i.state[207:206]	No	No		No		INPUT
lc_otp_program_i.state[209:208]	Yes	Yes	T71,T207,T214	Yes	T207,T215,T223	INPUT
lc_otp_program_i.state[218:210]	No	No		No		INPUT
lc_otp_program_i.state[219]	Yes	Yes	*T71,*T207,*T214	Yes	T207,T215,T223	INPUT
lc_otp_program_i.state[222:220]	No	No		No		INPUT
lc_otp_program_i.state[223]	Yes	Yes	*T71,*T207,*T214	Yes	T207,T215,T223	INPUT
lc_otp_program_i.state[227:224]	No	No		No		INPUT
lc_otp_program_i.state[228]	Yes	Yes	*T71,*T207,*T214	Yes	T207,T150,T223	INPUT
lc_otp_program_i.state[231:229]	No	No		No		INPUT
lc_otp_program_i.state[234:232]	Yes	Yes	T71,T207,T214	Yes	T207,T150,T223	INPUT
lc_otp_program_i.state[244:235]	No	No		No		INPUT
lc_otp_program_i.state[245]	Yes	Yes	*T71,*T214,*T220	Yes	T7,T213,T150	INPUT
lc_otp_program_i.state[247:246]	No	No		No		INPUT
lc_otp_program_i.state[250:248]	Yes	Yes	T71,T214,T220	Yes	T7,T213,T150	INPUT
lc_otp_program_i.state[251]	No	No		No		INPUT
lc_otp_program_i.state[252]	Yes	Yes	*T71,*T214,*T220	Yes	T7,T213,T150	INPUT
lc_otp_program_i.state[253]	No	No		No		INPUT
lc_otp_program_i.state[254]	Yes	Yes	*T71,*T214,*T220	Yes	T7,T213,T150	INPUT
lc_otp_program_i.state[258:255]	No	No		No		INPUT
lc_otp_program_i.state[259]	Yes	Yes	*T71,*T214,*T220	Yes	T7,T213,T150	INPUT
lc_otp_program_i.state[262:260]	No	No		No		INPUT
lc_otp_program_i.state[263]	Yes	Yes	*T71,*T214,*T220	Yes	T7,T213,T150	INPUT
lc_otp_program_i.state[265:264]	No	No		No		INPUT
lc_otp_program_i.state[267:266]	Yes	Yes	T71,T214,T220	Yes	T7,T213,T150	INPUT
lc_otp_program_i.state[269:268]	No	No		No		INPUT
lc_otp_program_i.state[270]	Yes	Yes	*T71,*T214,*T220	Yes	T7,T213,T150	INPUT
lc_otp_program_i.state[276:271]	No	No		No		INPUT
lc_otp_program_i.state[277]	Yes	Yes	*T71,*T214,*T221	Yes	T213,T150,T216	INPUT
lc_otp_program_i.state[280:278]	No	No		No		INPUT
lc_otp_program_i.state[281]	Yes	Yes	*T71,*T214,*T221	Yes	T213,T150,T216	INPUT
lc_otp_program_i.state[282]	No	No		No		INPUT
lc_otp_program_i.state[283]	Yes	Yes	*T71,*T214,*T221	Yes	T213,T150,T216	INPUT
lc_otp_program_i.state[288:284]	No	No		No		INPUT
lc_otp_program_i.state[292:289]	Yes	Yes	T71,T214,T221	Yes	T71,T150,T214	INPUT
lc_otp_program_i.state[297:293]	No	No		No		INPUT
lc_otp_program_i.state[298]	Yes	Yes	*T71,*T214,*T221	Yes	T71,T150,T214	INPUT
lc_otp_program_i.state[308:299]	No	No		No		INPUT
lc_otp_program_i.state[311:309]	Yes	Yes	T221,T224	Yes	T150,T225,T226	INPUT
lc_otp_program_i.state[313:312]	No	No		No		INPUT
lc_otp_program_i.state[314]	Yes	Yes	*T221,*T224	Yes	T150,T225,T226	INPUT
lc_otp_program_i.state[319:315]	No	No		No		INPUT
lc_otp_program_i.req	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	INPUT
lc_otp_program_o.ack	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	OUTPUT
lc_otp_program_o.err	No	No		No		OUTPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T8,T21	Yes	T1,T8,T21	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T1,T17,T4	Yes	T2,T3,T18	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T17,T5,T46	Yes	T3,T11,T12	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T1,T9,T8	Yes	T1,T9,T8	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
otp_lc_data_o.rma_token[127:0]	Yes	Yes	T44,T227,T228	Yes	T44,T227,T228	OUTPUT
otp_lc_data_o.rma_token_valid[3:0]	Yes	Yes	T4,T65,T69	Yes	T4,T7,T29	OUTPUT
otp_lc_data_o.test_exit_token[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_unlock_token[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_tokens_valid[3:0]	Yes	Yes	T2,T17,T18	Yes	T2,T17,T18	OUTPUT
otp_lc_data_o.secrets_valid[3:0]	Yes	Yes	T4,T65,T69	Yes	T4,T7,T29	OUTPUT
otp_lc_data_o.count[0]	No	No		No		OUTPUT
otp_lc_data_o.count[15:1]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[16]	No	No		No		OUTPUT
otp_lc_data_o.count[41:17]	Yes	Yes	*T6,*T71,*T72	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[42]	No	No		No		OUTPUT
otp_lc_data_o.count[51:43]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[52]	No	No		No		OUTPUT
otp_lc_data_o.count[54:53]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[55]	No	No		No		OUTPUT
otp_lc_data_o.count[61:56]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[65:62]	No	No		No		OUTPUT
otp_lc_data_o.count[84:66]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[85]	No	No		No		OUTPUT
otp_lc_data_o.count[100:86]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[101]	No	No		No		OUTPUT
otp_lc_data_o.count[105:102]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[106]	No	No		No		OUTPUT
otp_lc_data_o.count[115:107]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[116]	No	No		No		OUTPUT
otp_lc_data_o.count[121:117]	Yes	Yes	*T6,*T71,*T72	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[122]	No	No		No		OUTPUT
otp_lc_data_o.count[137:123]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[139:138]	No	No		No		OUTPUT
otp_lc_data_o.count[142:140]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[143]	No	No		No		OUTPUT
otp_lc_data_o.count[150:144]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[151]	No	No		No		OUTPUT
otp_lc_data_o.count[152]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[153]	No	No		No		OUTPUT
otp_lc_data_o.count[158:154]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[160:159]	No	No		No		OUTPUT
otp_lc_data_o.count[164:161]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[165]	No	No		No		OUTPUT
otp_lc_data_o.count[174:166]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[175]	No	No		No		OUTPUT
otp_lc_data_o.count[185:176]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[187:186]	No	No		No		OUTPUT
otp_lc_data_o.count[188]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[189]	No	No		No		OUTPUT
otp_lc_data_o.count[191:190]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[192]	No	No		No		OUTPUT
otp_lc_data_o.count[196:193]	Yes	Yes	*T6,*T71,*T72	Yes	T5,T6,T70	OUTPUT
otp_lc_data_o.count[197]	No	No		No		OUTPUT
otp_lc_data_o.count[198]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[199]	No	No		No		OUTPUT
otp_lc_data_o.count[206:200]	Yes	Yes	*T6,*T71,*T72	Yes	T5,T6,T70	OUTPUT
otp_lc_data_o.count[207]	No	No		No		OUTPUT
otp_lc_data_o.count[215:208]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[216]	No	No		No		OUTPUT
otp_lc_data_o.count[217]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[218]	No	No		No		OUTPUT
otp_lc_data_o.count[225:219]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[226]	No	No		No		OUTPUT
otp_lc_data_o.count[228:227]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[229]	No	No		No		OUTPUT
otp_lc_data_o.count[232:230]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[233]	No	No		No		OUTPUT
otp_lc_data_o.count[237:234]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[238]	No	No		No		OUTPUT
otp_lc_data_o.count[244:239]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[245]	No	No		No		OUTPUT
otp_lc_data_o.count[251:246]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[252]	No	No		No		OUTPUT
otp_lc_data_o.count[254:253]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[255]	No	No		No		OUTPUT
otp_lc_data_o.count[257:256]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[258]	No	No		No		OUTPUT
otp_lc_data_o.count[263:259]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[264]	No	No		No		OUTPUT
otp_lc_data_o.count[269:265]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[270]	No	No		No		OUTPUT
otp_lc_data_o.count[274:271]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[275]	No	No		No		OUTPUT
otp_lc_data_o.count[284:276]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[285]	No	No		No		OUTPUT
otp_lc_data_o.count[292:286]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[293]	No	No		No		OUTPUT
otp_lc_data_o.count[303:294]	Yes	Yes	*T6,*T72,*T229	Yes	T6,T72,T230	OUTPUT
otp_lc_data_o.count[304]	No	No		No		OUTPUT
otp_lc_data_o.count[309:305]	Yes	Yes	*T6,*T72,*T229	Yes	T6,T72,T230	OUTPUT
otp_lc_data_o.count[310]	No	No		No		OUTPUT
otp_lc_data_o.count[312:311]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[313]	No	No		No		OUTPUT
otp_lc_data_o.count[316:314]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[317]	No	No		No		OUTPUT
otp_lc_data_o.count[324:318]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[325]	No	No		No		OUTPUT
otp_lc_data_o.count[327:326]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[328]	No	No		No		OUTPUT
otp_lc_data_o.count[330:329]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[331]	No	No		No		OUTPUT
otp_lc_data_o.count[335:332]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[336]	No	No		No		OUTPUT
otp_lc_data_o.count[345:337]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[346]	No	No		No		OUTPUT
otp_lc_data_o.count[364:347]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[365]	No	No		No		OUTPUT
otp_lc_data_o.count[371:366]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[372]	No	No		No		OUTPUT
otp_lc_data_o.count[380:373]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[381]	No	No		No		OUTPUT
otp_lc_data_o.count[383:382]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[9:0]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[10]	No	No		No		OUTPUT
otp_lc_data_o.state[12:11]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[13]	No	No		No		OUTPUT
otp_lc_data_o.state[14]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[15]	No	No		No		OUTPUT
otp_lc_data_o.state[17:16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[18]	No	No		No		OUTPUT
otp_lc_data_o.state[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[20]	No	No		No		OUTPUT
otp_lc_data_o.state[21]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[22]	No	No		No		OUTPUT
otp_lc_data_o.state[34:23]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[37:35]	No	No		No		OUTPUT
otp_lc_data_o.state[42:38]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[43]	No	No		No		OUTPUT
otp_lc_data_o.state[46:44]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[48:47]	No	No		No		OUTPUT
otp_lc_data_o.state[51:49]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[52]	No	No		No		OUTPUT
otp_lc_data_o.state[79:53]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[80]	No	No		No		OUTPUT
otp_lc_data_o.state[83:81]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[85:84]	No	No		No		OUTPUT
otp_lc_data_o.state[87:86]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[88]	No	No		No		OUTPUT
otp_lc_data_o.state[98:89]	Yes	Yes	*T69,*T71,*T104	Yes	T7,T69,T231	OUTPUT
otp_lc_data_o.state[99]	No	No		No		OUTPUT
otp_lc_data_o.state[101:100]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[102]	No	No		No		OUTPUT
otp_lc_data_o.state[103]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[104]	No	No		No		OUTPUT
otp_lc_data_o.state[114:105]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[115]	No	No		No		OUTPUT
otp_lc_data_o.state[121:116]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[122]	No	No		No		OUTPUT
otp_lc_data_o.state[126:123]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[127]	No	No		No		OUTPUT
otp_lc_data_o.state[132:128]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[133]	No	No		No		OUTPUT
otp_lc_data_o.state[134]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[135]	No	No		No		OUTPUT
otp_lc_data_o.state[136]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[137]	No	No		No		OUTPUT
otp_lc_data_o.state[145:138]	Yes	Yes	*T69,*T71,*T207	Yes	T7,T69,T71	OUTPUT
otp_lc_data_o.state[146]	No	No		No		OUTPUT
otp_lc_data_o.state[149:147]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[150]	No	No		No		OUTPUT
otp_lc_data_o.state[151]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[152]	No	No		No		OUTPUT
otp_lc_data_o.state[153]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[154]	No	No		No		OUTPUT
otp_lc_data_o.state[157:155]	Yes	Yes	*T69,*T71,*T207	Yes	T7,T69,T71	OUTPUT
otp_lc_data_o.state[158]	No	No		No		OUTPUT
otp_lc_data_o.state[181:159]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[183:182]	No	No		No		OUTPUT
otp_lc_data_o.state[198:184]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[199]	No	No		No		OUTPUT
otp_lc_data_o.state[206:200]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[207]	No	No		No		OUTPUT
otp_lc_data_o.state[210:208]	Yes	Yes	T71,T216,T214	Yes	T7,T71,T150	OUTPUT
otp_lc_data_o.state[211]	No	No		No		OUTPUT
otp_lc_data_o.state[215:212]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[216]	No	No		No		OUTPUT
otp_lc_data_o.state[217]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[218]	No	No		No		OUTPUT
otp_lc_data_o.state[219]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[221:220]	No	No		No		OUTPUT
otp_lc_data_o.state[235:222]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[236]	No	No		No		OUTPUT
otp_lc_data_o.state[246:237]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[247]	No	No		No		OUTPUT
otp_lc_data_o.state[260:248]	Yes	Yes	*T71,*T216,*T214	Yes	T71,T150,T216	OUTPUT
otp_lc_data_o.state[261]	No	No		No		OUTPUT
otp_lc_data_o.state[268:262]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[269]	No	No		No		OUTPUT
otp_lc_data_o.state[273:270]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[274]	No	No		No		OUTPUT
otp_lc_data_o.state[277:275]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[280:278]	No	No		No		OUTPUT
otp_lc_data_o.state[294:281]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[295]	No	No		No		OUTPUT
otp_lc_data_o.state[306:296]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[308:307]	No	No		No		OUTPUT
otp_lc_data_o.state[309]	No	No		Yes	T150,T232	OUTPUT
otp_lc_data_o.state[310]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[311]	No	No		Yes	T150,T232	OUTPUT
otp_lc_data_o.state[312]	No	No		No		OUTPUT
otp_lc_data_o.state[319:313]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_keymgr_key_o.owner_seed_valid	No	No		No		OUTPUT
otp_keymgr_key_o.owner_seed[255:0]	No	No		No		OUTPUT
otp_keymgr_key_o.creator_seed_valid	No	No		No		OUTPUT
otp_keymgr_key_o.creator_seed[255:0]	No	No		No		OUTPUT
otp_keymgr_key_o.creator_root_key_share1_valid	Yes	Yes	T4,T65,T69	Yes	T4,T7,T29	OUTPUT
otp_keymgr_key_o.creator_root_key_share1[183:0]	Yes	Yes	*T63,*T69,*T45	Yes	T45,T87,T233	OUTPUT
otp_keymgr_key_o.creator_root_key_share1[184]	No	Yes	*T215,*T234,*T235	No		OUTPUT
otp_keymgr_key_o.creator_root_key_share1[255:185]	Yes	Yes	T1,T17,T19	Yes	T1,T17,T19	OUTPUT
otp_keymgr_key_o.creator_root_key_share0_valid	Yes	Yes	T4,T65,T69	Yes	T4,T7,T29	OUTPUT
otp_keymgr_key_o.creator_root_key_share0[47:0]	Yes	Yes	*T234,*T236,*T87	Yes	T87,T233,T237	OUTPUT
otp_keymgr_key_o.creator_root_key_share0[48]	No	No		Yes	T238,T236	OUTPUT
otp_keymgr_key_o.creator_root_key_share0[255:49]	Yes	Yes	T1,T17,T19	Yes	T1,T17,T19	OUTPUT
flash_otp_key_i.addr_req	Yes	Yes	T4,T5,T8	Yes	T4,T5,T8	INPUT
flash_otp_key_i.data_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
flash_otp_key_o.seed_valid	Yes	Yes	T150,T227,T239	Yes	T5,T29,T63	OUTPUT
flash_otp_key_o.rand_key[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
flash_otp_key_o.key[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
flash_otp_key_o.addr_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
flash_otp_key_o.data_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_i[0].req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
sram_otp_key_i[1].req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
sram_otp_key_i[2].req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
sram_otp_key_i[3].req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
sram_otp_key_o[0].seed_valid	Yes	Yes	T150,T227,T239	Yes	T5,T29,T63	OUTPUT
sram_otp_key_o[0].nonce[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[0].key[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[0].ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[1].seed_valid	Yes	Yes	T150,T227,T239	Yes	T5,T29,T63	OUTPUT
sram_otp_key_o[1].nonce[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[1].key[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[1].ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[2].seed_valid	Yes	Yes	T150,T227,T239	Yes	T5,T29,T63	OUTPUT
sram_otp_key_o[2].nonce[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[2].key[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[2].ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[3].seed_valid	Yes	Yes	T150,T227,T239	Yes	T5,T29,T63	OUTPUT
sram_otp_key_o[3].nonce[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[3].key[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[3].ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_otp_key_i.req	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
otbn_otp_key_o.seed_valid	Yes	Yes	T150,T227,T239	Yes	T5,T29,T63	OUTPUT
otbn_otp_key_o.nonce[63:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_otp_key_o.key[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_otp_key_o.ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otp_broadcast_o.hw_cfg0_data.device_id[255:0]	Yes	Yes	T25,T240,T241	Yes	T63,T71,T25	OUTPUT
otp_broadcast_o.hw_cfg0_data.manuf_state[255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.en_sram_ifetch[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.en_csrng_sw_app_read[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.en_entropy_src_fw_read[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.en_entropy_src_fw_over[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.unallocated[31:0]	Yes	Yes	T30,T68,T103	Yes	T64,T30,T68	OUTPUT
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.valid[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_ext_voltage_h_io	No	No		No		INOUT
scan_en_i	Yes	Yes	T9,T4,T5	Yes	T1,T18,T5	INPUT
scan_rst_ni	Yes	Yes	T3,T4,T46	Yes	T9,T5,T7	INPUT
scanmode_i[3:0]	Yes	Yes	T2,T4,T19	Yes	T1,T18,T33	INPUT
cio_test_o[7:0]	No	No		No		OUTPUT
cio_test_en_o[7:0]	Yes	Yes	T13,T10,T90	Yes	T11,T12,T13	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : otp_ctrl

	Line No.	Total	Covered	Percent
Branches		25	24	96.00
TERNARY	1404	2	2	100.00
TERNARY	1406	2	2	100.00
TERNARY	1408	2	2	100.00
IF	267	3	2	66.67
IF	288	2	2	100.00
IF	314	2	2	100.00
IF	375	2	2	100.00
IF	413	2	2	100.00
IF	434	2	2	100.00
IF	437	2	2	100.00
IF	464	2	2	100.00
IF	956	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1404	((part_digest[Secret0Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1406	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1408	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	267	if (tlul_req)
-2-:	268	if ((tlul_part_sel_oh != '0))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	314	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	375	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	413	if (otp_ctrl_part_pkg::PartInfo[k].integrity)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	434	if ((fatal_macro_error_q || fatal_check_error_q))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	956	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	67	67	100.00	65	97.01
Cover properties	0	0		0
Cover sequences	0	0		0
Total	67	67	100.00	65	97.01

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	26050016	25806694	0	0
CoreTlOutKnown_A	26050016	25806694	0	0
CreatorRootKeyShare0Size_A	552	552	0	0
CreatorRootKeyShare1Size_A	552	552	0	0
ErrorCodeWidth_A	552	552	0	0
FlashAddrKeySeedSize_A	552	552	0	0
FlashDataKeySeedSize_A	552	552	0	0
FlashOtpKeyRspKnown_A	26050016	25806694	0	0
FpvSecCmCntCnstyCheck_A	26050016	50	0	0
FpvSecCmCntDaiCheck_A	26050016	50	0	0
FpvSecCmCntIntegCheck_A	26050016	50	0	0
FpvSecCmCntKdiEntropyCheck_A	26050016	50	0	0
FpvSecCmCntKdiSeedCheck_A	26050016	50	0	0
FpvSecCmCntLciCheck_A	26050016	50	0	0
FpvSecCmCntScrmblCheck_A	26050016	50	0	0
FpvSecCmCtrlDaiFsmCheck_A	26050016	50	0	0
FpvSecCmCtrlKdiFsmCheck_A	26050016	50	0	0
FpvSecCmCtrlLciFsmCheck_A	26050016	50	0	0
FpvSecCmCtrlLfsrTimerFsmCheck_A	26050016	50	0	0
FpvSecCmCtrlScrambleFsmCheck_A	26050016	50	0	0
FpvSecCmDoubleLfsrCheck_A	26050016	50	0	0
FpvSecCmRegWeOnehotCheck_A	26050016	50	0	0
FpvSecCmTlLcGateFsm_A	26050016	50	0	0
IntrOtpErrorKnown_A	26050016	25806694	0	0
IntrOtpOperationDoneKnown_A	26050016	25806694	0	0
LcOtpProgramRspKnown_A	26050016	25806694	0	0
LcSeedHwRdEnStable0_A	26050016	96	0	0
LcSeedHwRdEnStable1_A	26050016	96	0	0
LcSeedHwRdEnStable2_A	26050016	0	0	0
LcSeedHwRdEnStable3_A	26050016	0	0	0
LcStateSize_A	552	552	0	0
LcTransitionCntSize_A	552	552	0	0
OtpAstPwrSeqKnown_A	26050016	25806694	0	0
OtpBroadcastKnown_A	26050016	25806694	0	0
OtpErrorCode0_A	552	552	0	0
OtpErrorCode1_A	552	552	0	0
OtpErrorCode2_A	552	552	0	0
OtpErrorCode3_A	552	552	0	0
OtpErrorCode4_A	552	552	0	0
OtpIfWidth_A	552	552	0	0
OtpKeymgrKeyKnown_A	26050016	25806694	0	0
OtpLcDataKnown_A	26050016	25806694	0	0
OtpOtgnKeyKnown_A	26050016	25806694	0	0
OtpRespFifoUnderflow_A	26050016	193327	0	0
OtpSramKeyKnown_A	26050016	25806694	0	0
PartSelMustBeOnehot_A	26050016	25806694	0	0
PrimTlOutKnown_A	26050016	25806694	0	0
PwrOtpInitRspKnown_A	26050016	25806694	0	0
RmaTokenSize_A	552	552	0	0
SramDataKeySeedSize_A	552	552	0	0
TestExitTokenSize_A	552	552	0	0
TestUnlockTokenSize_A	552	552	0	0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	26050016	50	0	0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	26050016	50	0	0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	26050016	50	0	0
gen_partitions[3].gen_buffered.FpvSecCmCntPartBufCheck_A	26050016	50	0	0
gen_partitions[3].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	26050016	50	0	0
gen_partitions[4].gen_buffered.FpvSecCmCntPartBufCheck_A	26050016	50	0	0
gen_partitions[4].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	26050016	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	26050016	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	26050016	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	26050016	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	26050016	50	0	0
gen_partitions[7].gen_lifecycle.FpvSecCmCntPartLcCheck_A	26050016	50	0	0
gen_partitions[7].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A	26050016	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	26050016	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	26050016	50	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

CoreTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

CreatorRootKeyShare0Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

CreatorRootKeyShare1Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

ErrorCodeWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

FlashAddrKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

FlashDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

FpvSecCmCntCnstyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCntDaiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCntIntegCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCntKdiEntropyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCntKdiSeedCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCntLciCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCntScrmblCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCtrlDaiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCtrlKdiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCtrlLciFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCtrlLfsrTimerFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCtrlScrambleFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmDoubleLfsrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

IntrOtpErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

IntrOtpOperationDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

LcOtpProgramRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

LcSeedHwRdEnStable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	96	0	0
T4	24955	1	0	0
T5	20141	0	0	0
T6	23159	0	0	0
T7	14644	1	0	0
T8	37926	0	0	0
T11	14160	0	0	0
T13	0	1	0	0
T19	14051	0	0	0
T20	12287	0	0	0
T29	0	1	0	0
T33	11519	0	0	0
T40	0	1	0	0
T46	12885	0	0	0
T65	0	2	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	3	0	0
T72	0	1	0	0

LcSeedHwRdEnStable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	96	0	0
T4	24955	1	0	0
T5	20141	0	0	0
T6	23159	0	0	0
T7	14644	1	0	0
T8	37926	0	0	0
T11	14160	0	0	0
T13	0	1	0	0
T19	14051	0	0	0
T20	12287	0	0	0
T29	0	1	0	0
T33	11519	0	0	0
T40	0	1	0	0
T46	12885	0	0	0
T65	0	2	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	3	0	0
T72	0	1	0	0

LcSeedHwRdEnStable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	0	0	0

LcSeedHwRdEnStable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	0	0	0

LcStateSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

LcTransitionCntSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtpAstPwrSeqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpBroadcastKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpErrorCode0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtpErrorCode1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtpErrorCode2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtpErrorCode3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtpErrorCode4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtpIfWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtpKeymgrKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpLcDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpOtgnKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpRespFifoUnderflow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	193327	0	0
T1	14672	105	0	0
T2	14654	217	0	0
T3	11603	172	0	0
T4	24955	456	0	0
T5	20141	395	0	0
T9	24294	145	0	0
T17	18877	257	0	0
T18	15607	201	0	0
T19	14051	180	0	0
T20	12287	155	0	0

OtpSramKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

PrimTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

PwrOtpInitRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

RmaTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

SramDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

TestExitTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

TestUnlockTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[3].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[3].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[4].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[4].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[7].gen_lifecycle.FpvSecCmCntPartLcCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[7].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		143	136	95.10
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
ALWAYS	264	14	13	92.86
ALWAYS	288	3	3	100.00
ALWAYS	304	7	7	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	362	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
ALWAYS	375	3	3	100.00
ALWAYS	399	19	19	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
ALWAYS	464	9	9	100.00
ALWAYS	486	10	10	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	607	1	1	100.00
CONT_ASSIGN	730	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
ALWAYS	841	2	2	100.00
ALWAYS	899	2	2	100.00
ALWAYS	926	4	4	100.00
CONT_ASSIGN	953	1	1	100.00
ALWAYS	956	3	3	100.00
CONT_ASSIGN	1008	1	1	100.00
CONT_ASSIGN	1010	1	1	100.00
CONT_ASSIGN	1044	1	1	100.00
CONT_ASSIGN	1095	1	0	0.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1265	1	0	0.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1301	1	1	100.00
ALWAYS	1313	2	2	100.00
CONT_ASSIGN	1327	1	1	100.00
ALWAYS	1355	9	9	100.00
CONT_ASSIGN	1386	1	1	100.00
CONT_ASSIGN	1387	1	1	100.00
CONT_ASSIGN	1389	1	1	100.00
CONT_ASSIGN	1391	1	1	100.00
CONT_ASSIGN	1395	1	1	100.00
CONT_ASSIGN	1397	1	1	100.00
CONT_ASSIGN	1399	1	1	100.00
CONT_ASSIGN	1404	1	1	100.00
CONT_ASSIGN	1406	1	1	100.00
CONT_ASSIGN	1408	1	1	100.00
CONT_ASSIGN	1440	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1446	1	1	100.00
CONT_ASSIGN	1450	1	1	100.00
CONT_ASSIGN	1454	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
234	8	8
264	1	1
265	1	1
266	1	1
267	1	1
268	1	1
269	1	1
272	0	1
			MISSING_ELSE
277	1	1
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
288	1	1
289	1	1
291	1	1
304	1	1
309	1	1
310	1	1
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
354	1	1
358	1	1
362	1	1
363	1	1
371	1	1
372	1	1
375	1	1
376	1	1
378	1	1
399	1	1
400	1	1
401	1	1
403	1	1
405	1	1
408	1	1
410	1	1
413	1	1
414	1	1
			MISSING_ELSE
418	1	1
420	1	1
424	1	1
427	1	1
429	1	1
434	1	1
435	1	1
			MISSING_ELSE
437	1	1
438	1	1
			MISSING_ELSE
443	1	1
453	1	1
461	1	1
464	1	1
465	1	1
466	1	1
467	1	1
468	1	1
470	1	1
471	1	1
472	1	1
473	1	1
486	1	1
488	1	1
490	1	1
492	1	1
494	1	1
503	1	1
505	1	1
506	1	1
507	1	1
508	1	1
550	1	1
558	1	1
605	1	1
607	1	1
730	1	1
731	1	1
732	1	1
762	1	1
764	1	1
841	1	1
842	1	1
899	1	1
900	1	1
926	1	1
927	1	1
928	1	1
929	1	1
953	1	1
956	1	1
957	1	1
959	1	1
1008	1	1
1010	1	1
1044	1	1
1095	0	1
1150	3	3
1205	0	4
1265	0	1
1277	1	1
1301	1	1
1313	1	1
1314	1	1
1327	1	1
1355	1	1
1356	1	1
1357	1	1
1358	1	1
1360	1	1
1361	1	1
1362	1	1
1363	1	1
1364	1	1
1386	1	1
1387	1	1
1389	1	1
1391	1	1
1395	1	1
1397	1	1
1399	1	1
1404	1	1
1406	1	1
1408	1	1
1440	1	1
1442	1	1
1446	1	1
1450	1	1
1454	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	101	89	88.12
Logical	101	89	88.12
Non-Logical	0	0
Event	0	0

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b0) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[0].PartEnd))
             --------------1-------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b01101100000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10
1	1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11010000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10
1	1	Covered	T10

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10
1	1	Covered	T10

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10
1	1	Covered	T10

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10
1	1	Covered	T10

 LINE       234
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10

 LINE       268
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       277
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       278
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       354
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       371
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       401
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Not Covered

 LINE       410
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       414
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T19,T20

 LINE       434
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T3,T19,T20

 LINE       443
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T2,T3,T17
0	0	1	0	Covered	T14,T15,T16
0	1	0	0	Covered	T14,T15,T16
1	0	0	0	Covered	T49

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T202
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T202

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T202
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T202

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T202
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T202

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T202
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T202

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T202
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T202

 LINE       605
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T4,T8

 LINE       607
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T4

 LINE       730
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       731
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       732
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       842
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1386
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T29

 LINE       1404
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T18

 LINE       1404
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T18

 LINE       1406
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T29

 LINE       1406
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T29

 LINE       1408
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T29

 LINE       1408
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T29

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	151	135	89.40
Total Bits	10856	8476	78.08
Total Bits 0->1	5428	4239	78.10
Total Bits 1->0	5428	4237	78.06

Ports	151	135	89.40
Port Bits	10856	8476	78.08
Port Bits 0->1	5428	4239	78.10
Port Bits 1->0	5428	4237	78.06

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_o.edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i.edn_fips	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i.edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
core_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T19	Yes	T1,T3,T19	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_error	Yes	Yes	T1,T9,T8	Yes	T1,T9,T8	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T9,T18	Yes	T1,T9,T18	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T18,T4	Yes	T3,T18,T4	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T1,T9,T4	Yes	T1,T9,T18	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T3,T18,T4	Yes	T3,T18,T4	INPUT
prim_tl_i.a_address[31:0]	Yes	Yes	T3,T4,T204	Yes	T3,T18,T4	INPUT
prim_tl_i.a_source[7:0]	Yes	Yes	T1,T18,T4	Yes	T1,T3,T18	INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T3,T4,T204	Yes	T3,T18,T4	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T1,T9,T18	Yes	T1,T9,T18	INPUT
prim_tl_i.a_valid	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
prim_tl_o.a_ready	Yes	Yes	T1,T11,T7	Yes	T1,T11,T7	OUTPUT
prim_tl_o.d_error	Yes	Yes	T11,T12,T13	Yes	T13,T10,T89	OUTPUT
prim_tl_o.d_user.data_intg[0]	Excluded	Excluded	*T13,*T206,*T90	Excluded	T13,T206,T90	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.data_intg[1]	Yes	Yes	*T13,*T206,*T90	Yes	T13,T206,T90	OUTPUT
prim_tl_o.d_user.data_intg[2]	Excluded	Excluded	*T13,*T206,*T90	Excluded	T13,T206,T90	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.data_intg[3]	Yes	Yes	*T13,*T206,*T90	Yes	T13,T206,T90	OUTPUT
prim_tl_o.d_user.data_intg[4]	Excluded	Excluded	*T206,*T90,*T91	Excluded	T206,T90,T91	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.data_intg[5]	Yes	Yes	*T13,*T206,*T90	Yes	T13,T206,T90	OUTPUT
prim_tl_o.d_user.data_intg[6]	Excluded	Excluded	T13,T206,T90	Excluded	T13,T206,T90	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.rsp_intg[5:0]	Excluded	Excluded	*T1,*T9,*T4	Excluded	T1,T9,T4	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T11,T12,T13	Yes	T13,T10,T206	OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	Yes	Yes	T1,T9,T5	Yes	T1,T9,T5	OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T10,T206,T89	Yes	T10,T206,T89	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T1,*T9,*T4	Yes	T1,T9,T4	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT
intr_otp_operation_done_o	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	OUTPUT
intr_otp_error_o	Yes	Yes	T2,T17,T46	Yes	T2,T17,T46	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T19,T20	Yes	T3,T19,T20	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T11,T12,T202	Yes	T11,T12,T202	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T11,T12,T202	Yes	T11,T12,T202	INPUT
alert_rx_i[3].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T11,T12,T202	Yes	T11,T12,T202	INPUT
alert_rx_i[4].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T19,T20	Yes	T3,T19,T20	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T11,T12,T202	Yes	T11,T12,T202	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T11,T12,T202	Yes	T11,T12,T202	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T11,T12,T202	Yes	T11,T12,T202	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0]	Yes	Yes	T4,T20,T33	Yes	T18,T5,T46	INPUT
pwr_otp_i.otp_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_otp_o.otp_idle	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_otp_o.otp_done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_otp_vendor_test_i.ctrl[31:0]	No	No		No		INPUT
lc_otp_vendor_test_o.status[31:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
lc_otp_program_i.count[16:0]	No	No		No		INPUT
lc_otp_program_i.count[17]	Yes	Yes	*T207,*T208,*T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[18]	No	No		No		INPUT
lc_otp_program_i.count[19]	Yes	Yes	*T207,*T208,*T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[21:20]	No	No		No		INPUT
lc_otp_program_i.count[22]	Yes	Yes	*T207,*T208,*T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[26:23]	No	No		No		INPUT
lc_otp_program_i.count[27]	Yes	Yes	*T207,*T208,*T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[33:28]	No	No		No		INPUT
lc_otp_program_i.count[35:34]	Yes	Yes	T207,T208,T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[36]	No	No		No		INPUT
lc_otp_program_i.count[37]	Yes	Yes	*T207,*T208,*T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[40:38]	No	No		No		INPUT
lc_otp_program_i.count[41]	Yes	Yes	*T207,*T208,*T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[42]	No	No		No		INPUT
lc_otp_program_i.count[43]	Yes	Yes	*T207,*T208,*T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[45:44]	No	No		No		INPUT
lc_otp_program_i.count[46]	Yes	Yes	*T207,*T208,*T209	Yes	T29,T207,T210	INPUT
lc_otp_program_i.count[48:47]	No	No		No		INPUT
lc_otp_program_i.count[49]	Yes	Yes	*T207,*T211,*T212	Yes	T29,T207,T213	INPUT
lc_otp_program_i.count[52:50]	No	No		No		INPUT
lc_otp_program_i.count[53]	Yes	Yes	*T207,*T211,*T212	Yes	T29,T207,T213	INPUT
lc_otp_program_i.count[55:54]	No	No		No		INPUT
lc_otp_program_i.count[56]	Yes	Yes	*T207,*T211,*T212	Yes	T29,T207,T213	INPUT
lc_otp_program_i.count[59:57]	No	No		No		INPUT
lc_otp_program_i.count[60]	Yes	Yes	*T207,*T211,*T212	Yes	T29,T207,T213	INPUT
lc_otp_program_i.count[65:61]	No	No		No		INPUT
lc_otp_program_i.count[66]	Yes	Yes	*T207,*T211,*T212	Yes	T29,T207,T213	INPUT
lc_otp_program_i.count[72:67]	No	No		No		INPUT
lc_otp_program_i.count[76:73]	Yes	Yes	T207,T211,T212	Yes	T29,T207,T213	INPUT
lc_otp_program_i.count[80:77]	No	No		No		INPUT
lc_otp_program_i.count[81]	Yes	Yes	*T207,*T210,*T212	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[82]	No	No		No		INPUT
lc_otp_program_i.count[84:83]	Yes	Yes	T207,T210,T212	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[87:85]	No	No		No		INPUT
lc_otp_program_i.count[88]	Yes	Yes	*T207,*T210,*T212	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[91:89]	No	No		No		INPUT
lc_otp_program_i.count[92]	Yes	Yes	*T207,*T210,*T212	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[93]	No	No		No		INPUT
lc_otp_program_i.count[94]	Yes	Yes	*T207,*T210,*T212	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[95]	No	No		No		INPUT
lc_otp_program_i.count[97:96]	Yes	Yes	T207,T210,T212	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[99:98]	No	No		No		INPUT
lc_otp_program_i.count[100]	Yes	Yes	*T207,*T210,*T212	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[108:101]	No	No		No		INPUT
lc_otp_program_i.count[110:109]	Yes	Yes	T207,T210,T212	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[116:111]	No	No		No		INPUT
lc_otp_program_i.count[118:117]	Yes	Yes	T6,T207,T214	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[122:119]	No	No		No		INPUT
lc_otp_program_i.count[123]	Yes	Yes	*T6,*T207,*T214	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[126:124]	No	No		No		INPUT
lc_otp_program_i.count[132:127]	Yes	Yes	T6,*T207,T214	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[136:133]	No	No		No		INPUT
lc_otp_program_i.count[137]	Yes	Yes	*T6,*T214,*T210	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[145:138]	No	No		No		INPUT
lc_otp_program_i.count[147:146]	Yes	Yes	T6,T214,T215	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[157:148]	No	No		No		INPUT
lc_otp_program_i.count[158]	Yes	Yes	*T6,*T214,*T215	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[160:159]	No	No		No		INPUT
lc_otp_program_i.count[162:161]	Yes	Yes	T6,T214,T215	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[163]	No	No		No		INPUT
lc_otp_program_i.count[164]	Yes	Yes	*T6,*T214,*T215	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[166:165]	No	No		No		INPUT
lc_otp_program_i.count[167]	Yes	Yes	*T6,*T214,*T215	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[168]	No	No		No		INPUT
lc_otp_program_i.count[169]	Yes	Yes	*T6,*T214,*T215	Yes	T29,T104,T207	INPUT
lc_otp_program_i.count[179:170]	No	No		No		INPUT
lc_otp_program_i.count[180]	Yes	Yes	*T6,*T71,*T214	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[182:181]	No	No		No		INPUT
lc_otp_program_i.count[184:183]	Yes	Yes	T6,T71,T214	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[189:185]	No	No		No		INPUT
lc_otp_program_i.count[190]	Yes	Yes	*T6,*T71,*T214	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[192:191]	No	No		No		INPUT
lc_otp_program_i.count[193]	Yes	Yes	*T6,*T71,*T214	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[195:194]	No	No		No		INPUT
lc_otp_program_i.count[196]	Yes	Yes	*T6,*T71,*T214	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[199:197]	No	No		No		INPUT
lc_otp_program_i.count[202:200]	Yes	Yes	T6,T71,T214	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[213:203]	No	No		No		INPUT
lc_otp_program_i.count[214]	Yes	Yes	*T6,*T71,*T72	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[220:215]	No	No		No		INPUT
lc_otp_program_i.count[222:221]	Yes	Yes	T6,T71,T72	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[223]	No	No		No		INPUT
lc_otp_program_i.count[224]	Yes	Yes	*T6,*T71,*T72	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[231:225]	No	No		No		INPUT
lc_otp_program_i.count[232]	Yes	Yes	*T6,*T71,*T72	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[234:233]	No	No		No		INPUT
lc_otp_program_i.count[235]	Yes	Yes	*T6,*T71,*T72	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[236]	No	No		No		INPUT
lc_otp_program_i.count[237]	Yes	Yes	*T6,*T71,*T72	Yes	T7,T29,T104	INPUT
lc_otp_program_i.count[245:238]	No	No		No		INPUT
lc_otp_program_i.count[246]	Yes	Yes	*T6,*T72,*T214	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[247]	No	No		No		INPUT
lc_otp_program_i.count[248]	Yes	Yes	*T6,*T72,*T214	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[249]	No	No		No		INPUT
lc_otp_program_i.count[251:250]	Yes	Yes	T6,T72,T214	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[255:252]	No	No		No		INPUT
lc_otp_program_i.count[257:256]	Yes	Yes	T6,T71,T72	Yes	T7,T70,T71	INPUT
lc_otp_program_i.count[259:258]	No	No		No		INPUT
lc_otp_program_i.count[260]	Yes	Yes	*T6,*T71,*T72	Yes	T7,T70,T71	INPUT
lc_otp_program_i.count[261]	No	No		No		INPUT
lc_otp_program_i.count[263:262]	Yes	Yes	T6,T71,T72	Yes	T7,T70,T71	INPUT
lc_otp_program_i.count[273:264]	No	No		No		INPUT
lc_otp_program_i.count[274]	Yes	Yes	*T6,*T72,*T215	Yes	T29,T100,T216	INPUT
lc_otp_program_i.count[278:275]	No	No		No		INPUT
lc_otp_program_i.count[280:279]	Yes	Yes	T6,T72,T215	Yes	T29,T100,T216	INPUT
lc_otp_program_i.count[286:281]	No	No		No		INPUT
lc_otp_program_i.count[287]	Yes	Yes	*T6,*T72,*T215	Yes	T29,T100,T216	INPUT
lc_otp_program_i.count[289:288]	No	No		No		INPUT
lc_otp_program_i.count[290]	Yes	Yes	*T6,*T72,*T210	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[293:291]	No	No		No		INPUT
lc_otp_program_i.count[294]	Yes	Yes	*T6,*T72,*T210	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[296:295]	No	No		No		INPUT
lc_otp_program_i.count[297]	Yes	Yes	*T6,*T72,*T210	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[299:298]	No	No		No		INPUT
lc_otp_program_i.count[300]	Yes	Yes	*T6,*T72,*T210	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[304:301]	No	No		No		INPUT
lc_otp_program_i.count[305]	Yes	Yes	*T6,*T72,*T210	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[307:306]	No	No		No		INPUT
lc_otp_program_i.count[309:308]	Yes	Yes	T6,T72,T210	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[315:310]	No	No		No		INPUT
lc_otp_program_i.count[316]	Yes	Yes	*T6,*T72,*T210	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[318:317]	No	No		No		INPUT
lc_otp_program_i.count[319]	Yes	Yes	*T6,*T72,*T210	Yes	T7,T70,T100	INPUT
lc_otp_program_i.count[339:320]	No	No		No		INPUT
lc_otp_program_i.count[341:340]	Yes	Yes	T212,T217	Yes	T218,T208,T219	INPUT
lc_otp_program_i.count[348:342]	No	No		No		INPUT
lc_otp_program_i.count[349]	Yes	Yes	*T212,*T217	Yes	T218,T208,T219	INPUT
lc_otp_program_i.count[350]	No	No		No		INPUT
lc_otp_program_i.count[353:351]	Yes	Yes	T212,T217,*T220	Yes	T218,T208,T219	INPUT
lc_otp_program_i.count[354]	No	No		No		INPUT
lc_otp_program_i.count[356:355]	Yes	Yes	T220,T212,T221	Yes	T29,T100,T222	INPUT
lc_otp_program_i.count[358:357]	No	No		No		INPUT
lc_otp_program_i.count[359]	Yes	Yes	*T220,*T212,*T221	Yes	T29,T100,T222	INPUT
lc_otp_program_i.count[368:360]	No	No		No		INPUT
lc_otp_program_i.count[369]	Yes	Yes	*T220,*T212,*T221	Yes	T29,T70,T72	INPUT
lc_otp_program_i.count[370]	No	No		No		INPUT
lc_otp_program_i.count[371]	Yes	Yes	*T220,*T212,*T221	Yes	T29,T70,T72	INPUT
lc_otp_program_i.count[372]	No	No		No		INPUT
lc_otp_program_i.count[374:373]	Yes	Yes	T220,T212,T221	Yes	T29,T70,T72	INPUT
lc_otp_program_i.count[383:375]	No	No		No		INPUT
lc_otp_program_i.state[4:0]	No	No		No		INPUT
lc_otp_program_i.state[5]	Yes	Yes	*T220,*T212,*T221	Yes	T29,T70,T72	INPUT
lc_otp_program_i.state[7:6]	No	No		No		INPUT
lc_otp_program_i.state[8]	Yes	Yes	*T220,*T212,*T221	Yes	T29,T70,T72	INPUT
lc_otp_program_i.state[10:9]	No	No		No		INPUT
lc_otp_program_i.state[12:11]	Yes	Yes	T220,T212,T221	Yes	T29,T70,T72	INPUT
lc_otp_program_i.state[22:13]	No	No		No		INPUT
lc_otp_program_i.state[24:23]	Yes	Yes	T71,T220,T210	Yes	T29,T72,T100	INPUT
lc_otp_program_i.state[28:25]	No	No		No		INPUT
lc_otp_program_i.state[30:29]	Yes	Yes	T71,T220,T210	Yes	T29,T72,T100	INPUT
lc_otp_program_i.state[37:31]	No	No		No		INPUT
lc_otp_program_i.state[38]	Yes	Yes	*T71,*T214,*T220	Yes	T6,T29,T72	INPUT
lc_otp_program_i.state[43:39]	No	No		No		INPUT
lc_otp_program_i.state[44]	Yes	Yes	*T71,*T214,*T220	Yes	T6,T29,T72	INPUT
lc_otp_program_i.state[45]	No	No		No		INPUT
lc_otp_program_i.state[46]	Yes	Yes	*T71,*T214,*T220	Yes	T6,T29,T72	INPUT
lc_otp_program_i.state[54:47]	No	No		No		INPUT
lc_otp_program_i.state[55]	Yes	Yes	*T71,*T214,*T220	Yes	T6,T29,T72	INPUT
lc_otp_program_i.state[62:56]	No	No		No		INPUT
lc_otp_program_i.state[63]	Yes	Yes	*T71,*T214,*T220	Yes	T6,T29,T72	INPUT
lc_otp_program_i.state[71:64]	No	No		No		INPUT
lc_otp_program_i.state[72]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[74:73]	No	No		No		INPUT
lc_otp_program_i.state[75]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[76]	No	No		No		INPUT
lc_otp_program_i.state[77]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[78]	No	No		No		INPUT
lc_otp_program_i.state[79]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[82:80]	No	No		No		INPUT
lc_otp_program_i.state[83]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[88:84]	No	No		No		INPUT
lc_otp_program_i.state[91:89]	Yes	Yes	T71,T214,T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[94:92]	No	No		No		INPUT
lc_otp_program_i.state[95]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[97:96]	No	No		No		INPUT
lc_otp_program_i.state[98]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[100:99]	No	No		No		INPUT
lc_otp_program_i.state[101]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[102]	No	No		No		INPUT
lc_otp_program_i.state[103]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[107:104]	No	No		No		INPUT
lc_otp_program_i.state[109:108]	Yes	Yes	T71,T214,T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[112:110]	No	No		No		INPUT
lc_otp_program_i.state[113]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[124:114]	No	No		No		INPUT
lc_otp_program_i.state[125]	Yes	Yes	*T71,*T214,*T220	Yes	T29,T72,T222	INPUT
lc_otp_program_i.state[128:126]	No	No		No		INPUT
lc_otp_program_i.state[131:129]	Yes	Yes	T71,T214,T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[137:132]	No	No		No		INPUT
lc_otp_program_i.state[138]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[139]	No	No		No		INPUT
lc_otp_program_i.state[141:140]	Yes	Yes	T71,T214,T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[144:142]	No	No		No		INPUT
lc_otp_program_i.state[145]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[148:146]	No	No		No		INPUT
lc_otp_program_i.state[149]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[150]	No	No		No		INPUT
lc_otp_program_i.state[151]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[154:152]	No	No		No		INPUT
lc_otp_program_i.state[156:155]	Yes	Yes	T71,T214,T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[159:157]	No	No		No		INPUT
lc_otp_program_i.state[160]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[162:161]	No	No		No		INPUT
lc_otp_program_i.state[163]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[166:164]	No	No		No		INPUT
lc_otp_program_i.state[167]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[168]	No	No		No		INPUT
lc_otp_program_i.state[169]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[172:170]	No	No		No		INPUT
lc_otp_program_i.state[173]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[174]	No	No		No		INPUT
lc_otp_program_i.state[175]	Yes	Yes	*T71,*T214,*T215	Yes	T29,T104,T222	INPUT
lc_otp_program_i.state[176]	No	No		No		INPUT
lc_otp_program_i.state[177]	Yes	Yes	*T71,*T207,*T214	Yes	T29,T104,T207	INPUT
lc_otp_program_i.state[179:178]	No	No		No		INPUT
lc_otp_program_i.state[180]	Yes	Yes	*T71,*T207,*T214	Yes	T29,T104,T207	INPUT
lc_otp_program_i.state[185:181]	No	No		No		INPUT
lc_otp_program_i.state[186]	Yes	Yes	*T71,*T207,*T214	Yes	T29,T104,T207	INPUT
lc_otp_program_i.state[188:187]	No	No		No		INPUT
lc_otp_program_i.state[189]	Yes	Yes	*T71,*T207,*T214	Yes	T29,T104,T207	INPUT
lc_otp_program_i.state[192:190]	No	No		No		INPUT
lc_otp_program_i.state[193]	Yes	Yes	*T71,*T207,*T214	Yes	T29,T207,T223	INPUT
lc_otp_program_i.state[195:194]	No	No		No		INPUT
lc_otp_program_i.state[196]	Yes	Yes	*T71,*T207,*T214	Yes	T29,T207,T223	INPUT
lc_otp_program_i.state[201:197]	No	No		No		INPUT
lc_otp_program_i.state[203:202]	Yes	Yes	T71,T207,T214	Yes	T29,T207,T223	INPUT
lc_otp_program_i.state[204]	No	No		No		INPUT
lc_otp_program_i.state[205]	Yes	Yes	*T71,*T207,*T214	Yes	T29,T207,T223	INPUT
lc_otp_program_i.state[207:206]	No	No		No		INPUT
lc_otp_program_i.state[209:208]	Yes	Yes	T71,T207,T214	Yes	T207,T215,T223	INPUT
lc_otp_program_i.state[218:210]	No	No		No		INPUT
lc_otp_program_i.state[219]	Yes	Yes	*T71,*T207,*T214	Yes	T207,T215,T223	INPUT
lc_otp_program_i.state[222:220]	No	No		No		INPUT
lc_otp_program_i.state[223]	Yes	Yes	*T71,*T207,*T214	Yes	T207,T215,T223	INPUT
lc_otp_program_i.state[227:224]	No	No		No		INPUT
lc_otp_program_i.state[228]	Yes	Yes	*T71,*T207,*T214	Yes	T207,T150,T223	INPUT
lc_otp_program_i.state[231:229]	No	No		No		INPUT
lc_otp_program_i.state[234:232]	Yes	Yes	T71,T207,T214	Yes	T207,T150,T223	INPUT
lc_otp_program_i.state[244:235]	No	No		No		INPUT
lc_otp_program_i.state[245]	Yes	Yes	*T71,*T214,*T220	Yes	T7,T213,T150	INPUT
lc_otp_program_i.state[247:246]	No	No		No		INPUT
lc_otp_program_i.state[250:248]	Yes	Yes	T71,T214,T220	Yes	T7,T213,T150	INPUT
lc_otp_program_i.state[251]	No	No		No		INPUT
lc_otp_program_i.state[252]	Yes	Yes	*T71,*T214,*T220	Yes	T7,T213,T150	INPUT
lc_otp_program_i.state[253]	No	No		No		INPUT
lc_otp_program_i.state[254]	Yes	Yes	*T71,*T214,*T220	Yes	T7,T213,T150	INPUT
lc_otp_program_i.state[258:255]	No	No		No		INPUT
lc_otp_program_i.state[259]	Yes	Yes	*T71,*T214,*T220	Yes	T7,T213,T150	INPUT
lc_otp_program_i.state[262:260]	No	No		No		INPUT
lc_otp_program_i.state[263]	Yes	Yes	*T71,*T214,*T220	Yes	T7,T213,T150	INPUT
lc_otp_program_i.state[265:264]	No	No		No		INPUT
lc_otp_program_i.state[267:266]	Yes	Yes	T71,T214,T220	Yes	T7,T213,T150	INPUT
lc_otp_program_i.state[269:268]	No	No		No		INPUT
lc_otp_program_i.state[270]	Yes	Yes	*T71,*T214,*T220	Yes	T7,T213,T150	INPUT
lc_otp_program_i.state[276:271]	No	No		No		INPUT
lc_otp_program_i.state[277]	Yes	Yes	*T71,*T214,*T221	Yes	T213,T150,T216	INPUT
lc_otp_program_i.state[280:278]	No	No		No		INPUT
lc_otp_program_i.state[281]	Yes	Yes	*T71,*T214,*T221	Yes	T213,T150,T216	INPUT
lc_otp_program_i.state[282]	No	No		No		INPUT
lc_otp_program_i.state[283]	Yes	Yes	*T71,*T214,*T221	Yes	T213,T150,T216	INPUT
lc_otp_program_i.state[288:284]	No	No		No		INPUT
lc_otp_program_i.state[292:289]	Yes	Yes	T71,T214,T221	Yes	T71,T150,T214	INPUT
lc_otp_program_i.state[297:293]	No	No		No		INPUT
lc_otp_program_i.state[298]	Yes	Yes	*T71,*T214,*T221	Yes	T71,T150,T214	INPUT
lc_otp_program_i.state[308:299]	No	No		No		INPUT
lc_otp_program_i.state[311:309]	Yes	Yes	T221,T224	Yes	T150,T225,T226	INPUT
lc_otp_program_i.state[313:312]	No	No		No		INPUT
lc_otp_program_i.state[314]	Yes	Yes	*T221,*T224	Yes	T150,T225,T226	INPUT
lc_otp_program_i.state[319:315]	No	No		No		INPUT
lc_otp_program_i.req	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	INPUT
lc_otp_program_o.ack	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	OUTPUT
lc_otp_program_o.err	No	No		No		OUTPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T8,T21	Yes	T1,T8,T21	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T1,T17,T4	Yes	T2,T3,T18	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T17,T5,T46	Yes	T3,T11,T12	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T1,T9,T8	Yes	T1,T9,T8	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
otp_lc_data_o.rma_token[127:0]	Yes	Yes	T44,T227,T228	Yes	T44,T227,T228	OUTPUT
otp_lc_data_o.rma_token_valid[3:0]	Yes	Yes	T4,T65,T69	Yes	T4,T7,T29	OUTPUT
otp_lc_data_o.test_exit_token[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_unlock_token[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_tokens_valid[3:0]	Yes	Yes	T2,T17,T18	Yes	T2,T17,T18	OUTPUT
otp_lc_data_o.secrets_valid[3:0]	Yes	Yes	T4,T65,T69	Yes	T4,T7,T29	OUTPUT
otp_lc_data_o.count[0]	No	No		No		OUTPUT
otp_lc_data_o.count[15:1]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[16]	No	No		No		OUTPUT
otp_lc_data_o.count[41:17]	Yes	Yes	*T6,*T71,*T72	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[42]	No	No		No		OUTPUT
otp_lc_data_o.count[51:43]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[52]	No	No		No		OUTPUT
otp_lc_data_o.count[54:53]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[55]	No	No		No		OUTPUT
otp_lc_data_o.count[61:56]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[65:62]	No	No		No		OUTPUT
otp_lc_data_o.count[84:66]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[85]	No	No		No		OUTPUT
otp_lc_data_o.count[100:86]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[101]	No	No		No		OUTPUT
otp_lc_data_o.count[105:102]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[106]	No	No		No		OUTPUT
otp_lc_data_o.count[115:107]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[116]	No	No		No		OUTPUT
otp_lc_data_o.count[121:117]	Yes	Yes	*T6,*T71,*T72	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[122]	No	No		No		OUTPUT
otp_lc_data_o.count[137:123]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[139:138]	No	No		No		OUTPUT
otp_lc_data_o.count[142:140]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[143]	No	No		No		OUTPUT
otp_lc_data_o.count[150:144]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[151]	No	No		No		OUTPUT
otp_lc_data_o.count[152]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[153]	No	No		No		OUTPUT
otp_lc_data_o.count[158:154]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[160:159]	No	No		No		OUTPUT
otp_lc_data_o.count[164:161]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[165]	No	No		No		OUTPUT
otp_lc_data_o.count[174:166]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[175]	No	No		No		OUTPUT
otp_lc_data_o.count[185:176]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[187:186]	No	No		No		OUTPUT
otp_lc_data_o.count[188]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[189]	No	No		No		OUTPUT
otp_lc_data_o.count[191:190]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[192]	No	No		No		OUTPUT
otp_lc_data_o.count[196:193]	Yes	Yes	*T6,*T71,*T72	Yes	T5,T6,T70	OUTPUT
otp_lc_data_o.count[197]	No	No		No		OUTPUT
otp_lc_data_o.count[198]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[199]	No	No		No		OUTPUT
otp_lc_data_o.count[206:200]	Yes	Yes	*T6,*T71,*T72	Yes	T5,T6,T70	OUTPUT
otp_lc_data_o.count[207]	No	No		No		OUTPUT
otp_lc_data_o.count[215:208]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[216]	No	No		No		OUTPUT
otp_lc_data_o.count[217]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[218]	No	No		No		OUTPUT
otp_lc_data_o.count[225:219]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[226]	No	No		No		OUTPUT
otp_lc_data_o.count[228:227]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[229]	No	No		No		OUTPUT
otp_lc_data_o.count[232:230]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[233]	No	No		No		OUTPUT
otp_lc_data_o.count[237:234]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[238]	No	No		No		OUTPUT
otp_lc_data_o.count[244:239]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[245]	No	No		No		OUTPUT
otp_lc_data_o.count[251:246]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[252]	No	No		No		OUTPUT
otp_lc_data_o.count[254:253]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[255]	No	No		No		OUTPUT
otp_lc_data_o.count[257:256]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[258]	No	No		No		OUTPUT
otp_lc_data_o.count[263:259]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[264]	No	No		No		OUTPUT
otp_lc_data_o.count[269:265]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[270]	No	No		No		OUTPUT
otp_lc_data_o.count[274:271]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[275]	No	No		No		OUTPUT
otp_lc_data_o.count[284:276]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[285]	No	No		No		OUTPUT
otp_lc_data_o.count[292:286]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[293]	No	No		No		OUTPUT
otp_lc_data_o.count[303:294]	Yes	Yes	*T6,*T72,*T229	Yes	T6,T72,T230	OUTPUT
otp_lc_data_o.count[304]	No	No		No		OUTPUT
otp_lc_data_o.count[309:305]	Yes	Yes	*T6,*T72,*T229	Yes	T6,T72,T230	OUTPUT
otp_lc_data_o.count[310]	No	No		No		OUTPUT
otp_lc_data_o.count[312:311]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[313]	No	No		No		OUTPUT
otp_lc_data_o.count[316:314]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[317]	No	No		No		OUTPUT
otp_lc_data_o.count[324:318]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[325]	No	No		No		OUTPUT
otp_lc_data_o.count[327:326]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[328]	No	No		No		OUTPUT
otp_lc_data_o.count[330:329]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[331]	No	No		No		OUTPUT
otp_lc_data_o.count[335:332]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[336]	No	No		No		OUTPUT
otp_lc_data_o.count[345:337]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[346]	No	No		No		OUTPUT
otp_lc_data_o.count[364:347]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.count[365]	No	No		No		OUTPUT
otp_lc_data_o.count[371:366]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[372]	No	No		No		OUTPUT
otp_lc_data_o.count[380:373]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[381]	No	No		No		OUTPUT
otp_lc_data_o.count[383:382]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[9:0]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[10]	No	No		No		OUTPUT
otp_lc_data_o.state[12:11]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[13]	No	No		No		OUTPUT
otp_lc_data_o.state[14]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[15]	No	No		No		OUTPUT
otp_lc_data_o.state[17:16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[18]	No	No		No		OUTPUT
otp_lc_data_o.state[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[20]	No	No		No		OUTPUT
otp_lc_data_o.state[21]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[22]	No	No		No		OUTPUT
otp_lc_data_o.state[34:23]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[37:35]	No	No		No		OUTPUT
otp_lc_data_o.state[42:38]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[43]	No	No		No		OUTPUT
otp_lc_data_o.state[46:44]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[48:47]	No	No		No		OUTPUT
otp_lc_data_o.state[51:49]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[52]	No	No		No		OUTPUT
otp_lc_data_o.state[79:53]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[80]	No	No		No		OUTPUT
otp_lc_data_o.state[83:81]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[85:84]	No	No		No		OUTPUT
otp_lc_data_o.state[87:86]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[88]	No	No		No		OUTPUT
otp_lc_data_o.state[98:89]	Yes	Yes	*T69,*T71,*T104	Yes	T7,T69,T231	OUTPUT
otp_lc_data_o.state[99]	No	No		No		OUTPUT
otp_lc_data_o.state[101:100]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[102]	No	No		No		OUTPUT
otp_lc_data_o.state[103]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[104]	No	No		No		OUTPUT
otp_lc_data_o.state[114:105]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[115]	No	No		No		OUTPUT
otp_lc_data_o.state[121:116]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[122]	No	No		No		OUTPUT
otp_lc_data_o.state[126:123]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[127]	No	No		No		OUTPUT
otp_lc_data_o.state[132:128]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[133]	No	No		No		OUTPUT
otp_lc_data_o.state[134]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[135]	No	No		No		OUTPUT
otp_lc_data_o.state[136]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[137]	No	No		No		OUTPUT
otp_lc_data_o.state[145:138]	Yes	Yes	*T69,*T71,*T207	Yes	T7,T69,T71	OUTPUT
otp_lc_data_o.state[146]	No	No		No		OUTPUT
otp_lc_data_o.state[149:147]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[150]	No	No		No		OUTPUT
otp_lc_data_o.state[151]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[152]	No	No		No		OUTPUT
otp_lc_data_o.state[153]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[154]	No	No		No		OUTPUT
otp_lc_data_o.state[157:155]	Yes	Yes	*T69,*T71,*T207	Yes	T7,T69,T71	OUTPUT
otp_lc_data_o.state[158]	No	No		No		OUTPUT
otp_lc_data_o.state[181:159]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[183:182]	No	No		No		OUTPUT
otp_lc_data_o.state[198:184]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[199]	No	No		No		OUTPUT
otp_lc_data_o.state[206:200]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[207]	No	No		No		OUTPUT
otp_lc_data_o.state[210:208]	Yes	Yes	T71,T216,T214	Yes	T7,T71,T150	OUTPUT
otp_lc_data_o.state[211]	No	No		No		OUTPUT
otp_lc_data_o.state[215:212]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[216]	No	No		No		OUTPUT
otp_lc_data_o.state[217]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[218]	No	No		No		OUTPUT
otp_lc_data_o.state[219]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[221:220]	No	No		No		OUTPUT
otp_lc_data_o.state[235:222]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[236]	No	No		No		OUTPUT
otp_lc_data_o.state[246:237]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[247]	No	No		No		OUTPUT
otp_lc_data_o.state[260:248]	Yes	Yes	*T71,*T216,*T214	Yes	T71,T150,T216	OUTPUT
otp_lc_data_o.state[261]	No	No		No		OUTPUT
otp_lc_data_o.state[268:262]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
otp_lc_data_o.state[269]	No	No		No		OUTPUT
otp_lc_data_o.state[273:270]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[274]	No	No		No		OUTPUT
otp_lc_data_o.state[277:275]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[280:278]	No	No		No		OUTPUT
otp_lc_data_o.state[294:281]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[295]	No	No		No		OUTPUT
otp_lc_data_o.state[306:296]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[308:307]	No	No		No		OUTPUT
otp_lc_data_o.state[309]	No	No		Yes	T150,T232	OUTPUT
otp_lc_data_o.state[310]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.state[311]	No	No		Yes	T150,T232	OUTPUT
otp_lc_data_o.state[312]	No	No		No		OUTPUT
otp_lc_data_o.state[319:313]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_keymgr_key_o.owner_seed_valid	No	No		No		OUTPUT
otp_keymgr_key_o.owner_seed[255:0]	No	No		No		OUTPUT
otp_keymgr_key_o.creator_seed_valid	No	No		No		OUTPUT
otp_keymgr_key_o.creator_seed[255:0]	No	No		No		OUTPUT
otp_keymgr_key_o.creator_root_key_share1_valid	Yes	Yes	T4,T65,T69	Yes	T4,T7,T29	OUTPUT
otp_keymgr_key_o.creator_root_key_share1[183:0]	Yes	Yes	*T63,*T69,*T45	Yes	T45,T87,T233	OUTPUT
otp_keymgr_key_o.creator_root_key_share1[184]	No	Yes	*T215,*T234,*T235	No		OUTPUT
otp_keymgr_key_o.creator_root_key_share1[255:185]	Yes	Yes	T1,T17,T19	Yes	T1,T17,T19	OUTPUT
otp_keymgr_key_o.creator_root_key_share0_valid	Yes	Yes	T4,T65,T69	Yes	T4,T7,T29	OUTPUT
otp_keymgr_key_o.creator_root_key_share0[47:0]	Yes	Yes	*T234,*T236,*T87	Yes	T87,T233,T237	OUTPUT
otp_keymgr_key_o.creator_root_key_share0[48]	No	No		Yes	T238,T236	OUTPUT
otp_keymgr_key_o.creator_root_key_share0[255:49]	Yes	Yes	T1,T17,T19	Yes	T1,T17,T19	OUTPUT
flash_otp_key_i.addr_req	Yes	Yes	T4,T5,T8	Yes	T4,T5,T8	INPUT
flash_otp_key_i.data_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
flash_otp_key_o.seed_valid	Yes	Yes	T150,T227,T239	Yes	T5,T29,T63	OUTPUT
flash_otp_key_o.rand_key[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
flash_otp_key_o.key[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
flash_otp_key_o.addr_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
flash_otp_key_o.data_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_i[0].req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
sram_otp_key_i[1].req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
sram_otp_key_i[2].req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
sram_otp_key_i[3].req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
sram_otp_key_o[0].seed_valid	Yes	Yes	T150,T227,T239	Yes	T5,T29,T63	OUTPUT
sram_otp_key_o[0].nonce[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[0].key[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[0].ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[1].seed_valid	Yes	Yes	T150,T227,T239	Yes	T5,T29,T63	OUTPUT
sram_otp_key_o[1].nonce[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[1].key[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[1].ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[2].seed_valid	Yes	Yes	T150,T227,T239	Yes	T5,T29,T63	OUTPUT
sram_otp_key_o[2].nonce[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[2].key[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[2].ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[3].seed_valid	Yes	Yes	T150,T227,T239	Yes	T5,T29,T63	OUTPUT
sram_otp_key_o[3].nonce[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[3].key[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
sram_otp_key_o[3].ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_otp_key_i.req	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
otbn_otp_key_o.seed_valid	Yes	Yes	T150,T227,T239	Yes	T5,T29,T63	OUTPUT
otbn_otp_key_o.nonce[63:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_otp_key_o.key[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otbn_otp_key_o.ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otp_broadcast_o.hw_cfg0_data.device_id[255:0]	Yes	Yes	T25,T240,T241	Yes	T63,T71,T25	OUTPUT
otp_broadcast_o.hw_cfg0_data.manuf_state[255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.en_sram_ifetch[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.en_csrng_sw_app_read[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.en_entropy_src_fw_read[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.en_entropy_src_fw_over[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.hw_cfg0_data.unallocated[31:0]	Yes	Yes	T30,T68,T103	Yes	T64,T30,T68	OUTPUT
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_broadcast_o.valid[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_ext_voltage_h_io	No	No		No		INOUT
scan_en_i	Yes	Yes	T9,T4,T5	Yes	T1,T18,T5	INPUT
scan_rst_ni	Yes	Yes	T3,T4,T46	Yes	T9,T5,T7	INPUT
scanmode_i[3:0]	Yes	Yes	T2,T4,T19	Yes	T1,T18,T33	INPUT
cio_test_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
cio_test_en_o[7:0]	Yes	Yes	T13,T10,T90	Yes	T11,T12,T13	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		25	24	96.00
TERNARY	1404	2	2	100.00
TERNARY	1406	2	2	100.00
TERNARY	1408	2	2	100.00
IF	267	3	2	66.67
IF	288	2	2	100.00
IF	314	2	2	100.00
IF	375	2	2	100.00
IF	413	2	2	100.00
IF	434	2	2	100.00
IF	437	2	2	100.00
IF	464	2	2	100.00
IF	956	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1404	((part_digest[Secret0Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1406	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1408	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	267	if (tlul_req)
-2-:	268	if ((tlul_part_sel_oh != '0))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	314	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	375	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	413	if (otp_ctrl_part_pkg::PartInfo[k].integrity)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	434	if ((fatal_macro_error_q || fatal_check_error_q))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	956	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	67	67	100.00	65	97.01
Cover properties	0	0		0
Cover sequences	0	0		0
Total	67	67	100.00	65	97.01

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	26050016	25806694	0	0
CoreTlOutKnown_A	26050016	25806694	0	0
CreatorRootKeyShare0Size_A	552	552	0	0
CreatorRootKeyShare1Size_A	552	552	0	0
ErrorCodeWidth_A	552	552	0	0
FlashAddrKeySeedSize_A	552	552	0	0
FlashDataKeySeedSize_A	552	552	0	0
FlashOtpKeyRspKnown_A	26050016	25806694	0	0
FpvSecCmCntCnstyCheck_A	26050016	50	0	0
FpvSecCmCntDaiCheck_A	26050016	50	0	0
FpvSecCmCntIntegCheck_A	26050016	50	0	0
FpvSecCmCntKdiEntropyCheck_A	26050016	50	0	0
FpvSecCmCntKdiSeedCheck_A	26050016	50	0	0
FpvSecCmCntLciCheck_A	26050016	50	0	0
FpvSecCmCntScrmblCheck_A	26050016	50	0	0
FpvSecCmCtrlDaiFsmCheck_A	26050016	50	0	0
FpvSecCmCtrlKdiFsmCheck_A	26050016	50	0	0
FpvSecCmCtrlLciFsmCheck_A	26050016	50	0	0
FpvSecCmCtrlLfsrTimerFsmCheck_A	26050016	50	0	0
FpvSecCmCtrlScrambleFsmCheck_A	26050016	50	0	0
FpvSecCmDoubleLfsrCheck_A	26050016	50	0	0
FpvSecCmRegWeOnehotCheck_A	26050016	50	0	0
FpvSecCmTlLcGateFsm_A	26050016	50	0	0
IntrOtpErrorKnown_A	26050016	25806694	0	0
IntrOtpOperationDoneKnown_A	26050016	25806694	0	0
LcOtpProgramRspKnown_A	26050016	25806694	0	0
LcSeedHwRdEnStable0_A	26050016	96	0	0
LcSeedHwRdEnStable1_A	26050016	96	0	0
LcSeedHwRdEnStable2_A	26050016	0	0	0
LcSeedHwRdEnStable3_A	26050016	0	0	0
LcStateSize_A	552	552	0	0
LcTransitionCntSize_A	552	552	0	0
OtpAstPwrSeqKnown_A	26050016	25806694	0	0
OtpBroadcastKnown_A	26050016	25806694	0	0
OtpErrorCode0_A	552	552	0	0
OtpErrorCode1_A	552	552	0	0
OtpErrorCode2_A	552	552	0	0
OtpErrorCode3_A	552	552	0	0
OtpErrorCode4_A	552	552	0	0
OtpIfWidth_A	552	552	0	0
OtpKeymgrKeyKnown_A	26050016	25806694	0	0
OtpLcDataKnown_A	26050016	25806694	0	0
OtpOtgnKeyKnown_A	26050016	25806694	0	0
OtpRespFifoUnderflow_A	26050016	193327	0	0
OtpSramKeyKnown_A	26050016	25806694	0	0
PartSelMustBeOnehot_A	26050016	25806694	0	0
PrimTlOutKnown_A	26050016	25806694	0	0
PwrOtpInitRspKnown_A	26050016	25806694	0	0
RmaTokenSize_A	552	552	0	0
SramDataKeySeedSize_A	552	552	0	0
TestExitTokenSize_A	552	552	0	0
TestUnlockTokenSize_A	552	552	0	0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	26050016	50	0	0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	26050016	50	0	0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	26050016	50	0	0
gen_partitions[3].gen_buffered.FpvSecCmCntPartBufCheck_A	26050016	50	0	0
gen_partitions[3].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	26050016	50	0	0
gen_partitions[4].gen_buffered.FpvSecCmCntPartBufCheck_A	26050016	50	0	0
gen_partitions[4].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	26050016	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	26050016	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	26050016	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	26050016	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	26050016	50	0	0
gen_partitions[7].gen_lifecycle.FpvSecCmCntPartLcCheck_A	26050016	50	0	0
gen_partitions[7].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A	26050016	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	26050016	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	26050016	50	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

CoreTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

CreatorRootKeyShare0Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

CreatorRootKeyShare1Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

ErrorCodeWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

FlashAddrKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

FlashDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

FpvSecCmCntCnstyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCntDaiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCntIntegCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCntKdiEntropyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCntKdiSeedCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCntLciCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCntScrmblCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCtrlDaiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCtrlKdiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCtrlLciFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCtrlLfsrTimerFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmCtrlScrambleFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmDoubleLfsrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

FpvSecCmTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

IntrOtpErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

IntrOtpOperationDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

LcOtpProgramRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

LcSeedHwRdEnStable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	96	0	0
T4	24955	1	0	0
T5	20141	0	0	0
T6	23159	0	0	0
T7	14644	1	0	0
T8	37926	0	0	0
T11	14160	0	0	0
T13	0	1	0	0
T19	14051	0	0	0
T20	12287	0	0	0
T29	0	1	0	0
T33	11519	0	0	0
T40	0	1	0	0
T46	12885	0	0	0
T65	0	2	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	3	0	0
T72	0	1	0	0

LcSeedHwRdEnStable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	96	0	0
T4	24955	1	0	0
T5	20141	0	0	0
T6	23159	0	0	0
T7	14644	1	0	0
T8	37926	0	0	0
T11	14160	0	0	0
T13	0	1	0	0
T19	14051	0	0	0
T20	12287	0	0	0
T29	0	1	0	0
T33	11519	0	0	0
T40	0	1	0	0
T46	12885	0	0	0
T65	0	2	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	3	0	0
T72	0	1	0	0

LcSeedHwRdEnStable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	0	0	0

LcSeedHwRdEnStable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	0	0	0

LcStateSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

LcTransitionCntSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtpAstPwrSeqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpBroadcastKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpErrorCode0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtpErrorCode1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtpErrorCode2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtpErrorCode3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtpErrorCode4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtpIfWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtpKeymgrKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpLcDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpOtgnKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpRespFifoUnderflow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	193327	0	0
T1	14672	105	0	0
T2	14654	217	0	0
T3	11603	172	0	0
T4	24955	456	0	0
T5	20141	395	0	0
T9	24294	145	0	0
T17	18877	257	0	0
T18	15607	201	0	0
T19	14051	180	0	0
T20	12287	155	0	0

OtpSramKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

PrimTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

PwrOtpInitRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

RmaTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

SramDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

TestExitTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

TestUnlockTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[3].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[3].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[4].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[4].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[7].gen_lifecycle.FpvSecCmCntPartLcCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_partitions[7].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	50	0	0
T14	106216	10	0	0
T15	103174	10	0	0
T16	0	10	0	0
T83	13853	0	0	0
T160	29031	0	0	0
T242	0	10	0	0
T243	0	10	0	0
T244	9118	0	0	0
T245	6282	0	0	0
T246	16945	0	0	0
T247	18865	0	0	0
T248	11755	0	0	0
T249	16941	0	0	0