Unified Coverage Report :: Module :: otp_ctrl_core_reg_top

Module : otp_ctrl_core_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	94.69			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_core	98.67	100.00	94.69			100.00	100.00

---

Module Instance : tb.dut.u_reg_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	94.69			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.15	99.60	96.17	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.86	95.10	88.12	78.08		96.00	97.01	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_bus_integ_error	100.00	100.00
u_alert_test_fatal_check_error	100.00	100.00
u_alert_test_fatal_macro_error	100.00	100.00
u_alert_test_fatal_prim_otp_alert	100.00	100.00
u_alert_test_recov_prim_otp_alert	100.00	100.00
u_check_regwen	100.00	100.00	100.00			100.00
u_check_timeout	100.00	100.00	100.00			100.00
u_check_trigger_consistency	100.00	100.00
u_check_trigger_integrity	100.00	100.00
u_check_trigger_regwen	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_consistency_check_period	100.00	100.00	100.00			100.00
u_creator_sw_cfg_digest_0	100.00	100.00
u_creator_sw_cfg_digest_1	100.00	100.00
u_creator_sw_cfg_read_lock	100.00	100.00	100.00			100.00
u_direct_access_address	100.00	100.00	100.00			100.00
u_direct_access_cmd_digest	100.00	100.00
u_direct_access_cmd_rd	100.00	100.00
u_direct_access_cmd_wr	100.00	100.00
u_direct_access_rdata_0	100.00	100.00
u_direct_access_rdata_1	100.00	100.00
u_direct_access_regwen	100.00	100.00
u_direct_access_wdata_0	100.00	100.00	100.00			100.00
u_direct_access_wdata_1	100.00	100.00	100.00			100.00
u_err_code_0	100.00	100.00
u_err_code_1	100.00	100.00
u_err_code_2	100.00	100.00
u_err_code_3	100.00	100.00
u_err_code_4	100.00	100.00
u_err_code_5	100.00	100.00
u_err_code_6	100.00	100.00
u_err_code_7	100.00	100.00
u_err_code_8	100.00	100.00
u_err_code_9	100.00	100.00
u_hw_cfg0_digest_0	100.00	100.00
u_hw_cfg0_digest_1	100.00	100.00
u_integrity_check_period	100.00	100.00	100.00			100.00
u_intr_enable_otp_error	100.00	100.00	100.00			100.00
u_intr_enable_otp_operation_done	100.00	100.00	100.00			100.00
u_intr_state_otp_error	100.00	100.00	100.00			100.00
u_intr_state_otp_operation_done	100.00	100.00	100.00			100.00
u_intr_test_otp_error	100.00	100.00
u_intr_test_otp_operation_done	100.00	100.00
u_owner_sw_cfg_digest_0	100.00	100.00
u_owner_sw_cfg_digest_1	100.00	100.00
u_owner_sw_cfg_read_lock	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_secret0_digest_0	100.00	100.00
u_secret0_digest_1	100.00	100.00
u_secret1_digest_0	100.00	100.00
u_secret1_digest_1	100.00	100.00
u_secret2_digest_0	100.00	100.00
u_secret2_digest_1	100.00	100.00
u_socket	99.24	98.75	98.21			100.00	100.00
u_status_bus_integ_error	100.00	100.00
u_status_check_pending	100.00	100.00
u_status_creator_sw_cfg_error	100.00	100.00
u_status_dai_error	100.00	100.00
u_status_dai_idle	100.00	100.00
u_status_hw_cfg0_error	100.00	100.00
u_status_key_deriv_fsm_error	100.00	100.00
u_status_lci_error	100.00	100.00
u_status_lfsr_fsm_error	100.00	100.00
u_status_life_cycle_error	100.00	100.00
u_status_owner_sw_cfg_error	100.00	100.00
u_status_scrambling_fsm_error	100.00	100.00
u_status_secret0_error	100.00	100.00
u_status_secret1_error	100.00	100.00
u_status_secret2_error	100.00	100.00
u_status_timeout_error	100.00	100.00
u_status_vendor_test_error	100.00	100.00
u_vendor_test_digest_0	100.00	100.00
u_vendor_test_digest_1	100.00	100.00
u_vendor_test_read_lock	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : otp_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
TOTAL		282	282	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	489	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
CONT_ASSIGN	986	1	1	100.00
CONT_ASSIGN	989	1	1	100.00
CONT_ASSIGN	1004	1	1	100.00
CONT_ASSIGN	1020	1	1	100.00
CONT_ASSIGN	1036	1	1	100.00
CONT_ASSIGN	1042	1	1	100.00
CONT_ASSIGN	1074	1	1	100.00
CONT_ASSIGN	1106	1	1	100.00
CONT_ASSIGN	1199	1	1	100.00
CONT_ASSIGN	1202	1	1	100.00
CONT_ASSIGN	1217	1	1	100.00
CONT_ASSIGN	1233	1	1	100.00
CONT_ASSIGN	1267	1	1	100.00
CONT_ASSIGN	1298	1	1	100.00
CONT_ASSIGN	1329	1	1	100.00
CONT_ASSIGN	1360	1	1	100.00
CONT_ASSIGN	1391	1	1	100.00
CONT_ASSIGN	1422	1	1	100.00
ALWAYS	1691	46	46	100.00
CONT_ASSIGN	1739	1	1	100.00
ALWAYS	1743	1	1	100.00
CONT_ASSIGN	1792	1	1	100.00
CONT_ASSIGN	1794	1	1	100.00
CONT_ASSIGN	1796	1	1	100.00
CONT_ASSIGN	1797	1	1	100.00
CONT_ASSIGN	1799	1	1	100.00
CONT_ASSIGN	1801	1	1	100.00
CONT_ASSIGN	1802	1	1	100.00
CONT_ASSIGN	1804	1	1	100.00
CONT_ASSIGN	1806	1	1	100.00
CONT_ASSIGN	1807	1	1	100.00
CONT_ASSIGN	1809	1	1	100.00
CONT_ASSIGN	1811	1	1	100.00
CONT_ASSIGN	1813	1	1	100.00
CONT_ASSIGN	1815	1	1	100.00
CONT_ASSIGN	1817	1	1	100.00
CONT_ASSIGN	1818	1	1	100.00
CONT_ASSIGN	1819	1	1	100.00
CONT_ASSIGN	1820	1	1	100.00
CONT_ASSIGN	1821	1	1	100.00
CONT_ASSIGN	1822	1	1	100.00
CONT_ASSIGN	1823	1	1	100.00
CONT_ASSIGN	1824	1	1	100.00
CONT_ASSIGN	1825	1	1	100.00
CONT_ASSIGN	1826	1	1	100.00
CONT_ASSIGN	1827	1	1	100.00
CONT_ASSIGN	1828	1	1	100.00
CONT_ASSIGN	1829	1	1	100.00
CONT_ASSIGN	1830	1	1	100.00
CONT_ASSIGN	1832	1	1	100.00
CONT_ASSIGN	1834	1	1	100.00
CONT_ASSIGN	1836	1	1	100.00
CONT_ASSIGN	1837	1	1	100.00
CONT_ASSIGN	1839	1	1	100.00
CONT_ASSIGN	1840	1	1	100.00
CONT_ASSIGN	1842	1	1	100.00
CONT_ASSIGN	1843	1	1	100.00
CONT_ASSIGN	1845	1	1	100.00
CONT_ASSIGN	1846	1	1	100.00
CONT_ASSIGN	1847	1	1	100.00
CONT_ASSIGN	1848	1	1	100.00
CONT_ASSIGN	1850	1	1	100.00
CONT_ASSIGN	1851	1	1	100.00
CONT_ASSIGN	1853	1	1	100.00
CONT_ASSIGN	1855	1	1	100.00
CONT_ASSIGN	1856	1	1	100.00
CONT_ASSIGN	1858	1	1	100.00
CONT_ASSIGN	1859	1	1	100.00
CONT_ASSIGN	1861	1	1	100.00
CONT_ASSIGN	1862	1	1	100.00
CONT_ASSIGN	1864	1	1	100.00
CONT_ASSIGN	1865	1	1	100.00
CONT_ASSIGN	1867	1	1	100.00
CONT_ASSIGN	1868	1	1	100.00
CONT_ASSIGN	1870	1	1	100.00
CONT_ASSIGN	1871	1	1	100.00
CONT_ASSIGN	1873	1	1	100.00
CONT_ASSIGN	1874	1	1	100.00
CONT_ASSIGN	1876	1	1	100.00
CONT_ASSIGN	1877	1	1	100.00
CONT_ASSIGN	1878	1	1	100.00
CONT_ASSIGN	1879	1	1	100.00
CONT_ASSIGN	1880	1	1	100.00
CONT_ASSIGN	1881	1	1	100.00
CONT_ASSIGN	1882	1	1	100.00
CONT_ASSIGN	1883	1	1	100.00
CONT_ASSIGN	1884	1	1	100.00
CONT_ASSIGN	1885	1	1	100.00
CONT_ASSIGN	1886	1	1	100.00
CONT_ASSIGN	1887	1	1	100.00
CONT_ASSIGN	1888	1	1	100.00
CONT_ASSIGN	1889	1	1	100.00
CONT_ASSIGN	1890	1	1	100.00
ALWAYS	1894	46	46	100.00
ALWAYS	1944	73	73	100.00
CONT_ASSIGN	2163	0	0
CONT_ASSIGN	2171	1	1	100.00
CONT_ASSIGN	2172	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
100	1	1
101	1	1
103	1	1
104	1	1
130	1	1
136	1	1
137	1	1
			MISSING_ELSE
167	1	1
168	1	1
421	1	1
436	1	1
452	1	1
458	1	1
473	1	1
489	1	1
505	1	1
521	1	1
537	1	1
986	1	1
989	1	1
1004	1	1
1020	1	1
1036	1	1
1042	1	1
1074	1	1
1106	1	1
1199	1	1
1202	1	1
1217	1	1
1233	1	1
1267	1	1
1298	1	1
1329	1	1
1360	1	1
1391	1	1
1422	1	1
1691	1	1
1692	1	1
1693	1	1
1694	1	1
1695	1	1
1696	1	1
1697	1	1
1698	1	1
1699	1	1
1700	1	1
1701	1	1
1702	1	1
1703	1	1
1704	1	1
1705	1	1
1706	1	1
1707	1	1
1708	1	1
1709	1	1
1710	1	1
1711	1	1
1712	1	1
1713	1	1
1714	1	1
1715	1	1
1716	1	1
1717	1	1
1718	1	1
1719	1	1
1720	1	1
1721	1	1
1722	1	1
1723	1	1
1724	1	1
1725	1	1
1726	1	1
1727	1	1
1728	1	1
1729	1	1
1730	1	1
1731	1	1
1732	1	1
1733	1	1
1734	1	1
1735	1	1
1736	1	1
1739	1	1
1743	1	1
1792	1	1
1794	1	1
1796	1	1
1797	1	1
1799	1	1
1801	1	1
1802	1	1
1804	1	1
1806	1	1
1807	1	1
1809	1	1
1811	1	1
1813	1	1
1815	1	1
1817	1	1
1818	1	1
1819	1	1
1820	1	1
1821	1	1
1822	1	1
1823	1	1
1824	1	1
1825	1	1
1826	1	1
1827	1	1
1828	1	1
1829	1	1
1830	1	1
1832	1	1
1834	1	1
1836	1	1
1837	1	1
1839	1	1
1840	1	1
1842	1	1
1843	1	1
1845	1	1
1846	1	1
1847	1	1
1848	1	1
1850	1	1
1851	1	1
1853	1	1
1855	1	1
1856	1	1
1858	1	1
1859	1	1
1861	1	1
1862	1	1
1864	1	1
1865	1	1
1867	1	1
1868	1	1
1870	1	1
1871	1	1
1873	1	1
1874	1	1
1876	1	1
1877	1	1
1878	1	1
1879	1	1
1880	1	1
1881	1	1
1882	1	1
1883	1	1
1884	1	1
1885	1	1
1886	1	1
1887	1	1
1888	1	1
1889	1	1
1890	1	1
1894	1	1
1895	1	1
1896	1	1
1897	1	1
1898	1	1
1899	1	1
1900	1	1
1901	1	1
1902	1	1
1903	1	1
1904	1	1
1905	1	1
1906	1	1
1907	1	1
1908	1	1
1909	1	1
1910	1	1
1911	1	1
1912	1	1
1913	1	1
1914	1	1
1915	1	1
1916	1	1
1917	1	1
1918	1	1
1919	1	1
1920	1	1
1921	1	1
1922	1	1
1923	1	1
1924	1	1
1925	1	1
1926	1	1
1927	1	1
1928	1	1
1929	1	1
1930	1	1
1931	1	1
1932	1	1
1933	1	1
1934	1	1
1935	1	1
1936	1	1
1937	1	1
1938	1	1
1939	1	1
1944	1	1
1945	1	1
1947	1	1
1948	1	1
1952	1	1
1953	1	1
1957	1	1
1958	1	1
1962	1	1
1963	1	1
1964	1	1
1965	1	1
1966	1	1
1970	1	1
1971	1	1
1972	1	1
1973	1	1
1974	1	1
1975	1	1
1976	1	1
1977	1	1
1978	1	1
1979	1	1
1980	1	1
1981	1	1
1982	1	1
1983	1	1
1984	1	1
1985	1	1
1986	1	1
1990	1	1
1994	1	1
1998	1	1
2002	1	1
2006	1	1
2010	1	1
2014	1	1
2018	1	1
2022	1	1
2026	1	1
2030	1	1
2034	1	1
2035	1	1
2036	1	1
2040	1	1
2044	1	1
2048	1	1
2052	1	1
2056	1	1
2060	1	1
2064	1	1
2065	1	1
2069	1	1
2073	1	1
2077	1	1
2081	1	1
2085	1	1
2089	1	1
2093	1	1
2097	1	1
2101	1	1
2105	1	1
2109	1	1
2113	1	1
2117	1	1
2121	1	1
2125	1	1
2129	1	1
2133	1	1
2137	1	1
2141	1	1
2145	1	1
2149	1	1
2163		unreachable
2171	1	1
2172	1	1

---

Cond Coverage for Module : otp_ctrl_core_reg_top

	Total	Covered	Percent
Conditions	508	481	94.69
Logical	508	481	94.69
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
63-1848	96.67
1851-1890	85.23

---

Branch Coverage for Module : otp_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	1739	2	2	100.00
IF	73	3	3	100.00
TERNARY	130	2	2	100.00
IF	136	2	2	100.00
CASE	1945	46	46	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1739	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T91,T93,T95
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	((tl_i.a_address[(AW - 1):0] inside {[4096:6143]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	136	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T91,T93,T95
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1945	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T2,T9,T17
addr_hit[3]	Covered	T1,T2,T9
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T9
addr_hit[6]	Covered	T1,T2,T9
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T9
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T9
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T9
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T9
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T9
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T9
addr_hit[25]	Covered	T1,T2,T9
addr_hit[26]	Covered	T2,T9,T17
addr_hit[27]	Covered	T2,T9,T17
addr_hit[28]	Covered	T1,T2,T9
addr_hit[29]	Covered	T1,T2,T9
addr_hit[30]	Covered	T1,T2,T9
addr_hit[31]	Covered	T1,T2,T9
addr_hit[32]	Covered	T1,T2,T9
addr_hit[33]	Covered	T1,T2,T9
addr_hit[34]	Covered	T1,T2,T9
addr_hit[35]	Covered	T1,T2,T9
addr_hit[36]	Covered	T1,T2,T9
addr_hit[37]	Covered	T1,T2,T9
addr_hit[38]	Covered	T1,T2,T9
addr_hit[39]	Covered	T1,T2,T9
addr_hit[40]	Covered	T1,T2,T9
addr_hit[41]	Covered	T1,T2,T9
addr_hit[42]	Covered	T1,T2,T9
addr_hit[43]	Covered	T1,T2,T9
addr_hit[44]	Covered	T1,T2,T9
default	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_core_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	28618019	778932	0	0
reAfterRv	28618019	778927	0	0
rePulse	28618019	578317	0	0
wePulse	28618019	200610	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	28618019	778932	0	0
T1	14672	1144	0	0
T2	14654	658	0	0
T3	11603	458	0	0
T4	24955	4088	0	0
T5	20141	2788	0	0
T9	24294	2352	0	0
T17	18877	836	0	0
T18	15607	680	0	0
T19	14051	820	0	0
T20	12287	465	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	28618019	778927	0	0
T1	14672	1144	0	0
T2	14654	658	0	0
T3	11603	458	0	0
T4	24955	4088	0	0
T5	20141	2788	0	0
T9	24294	2352	0	0
T17	18877	836	0	0
T18	15607	680	0	0
T19	14051	820	0	0
T20	12287	465	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	28618019	578317	0	0
T1	14672	978	0	0
T2	14654	415	0	0
T3	11603	289	0	0
T4	24955	3758	0	0
T5	20141	2508	0	0
T9	24294	2087	0	0
T17	18877	535	0	0
T18	15607	448	0	0
T19	14051	531	0	0
T20	12287	299	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	28618019	200610	0	0
T1	14672	166	0	0
T2	14654	243	0	0
T3	11603	169	0	0
T4	24955	330	0	0
T5	20141	280	0	0
T9	24294	265	0	0
T17	18877	301	0	0
T18	15607	232	0	0
T19	14051	289	0	0
T20	12287	166	0	0