Unified Coverage Report :: Module :: otp_ctrl_part_unbuf

Module : otp_ctrl_part_unbuf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.33	91.39	96.77		52.94	89.39	96.15

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf	81.09	87.50	93.55		48.00	84.09	92.31
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf	86.95	90.91	96.77		60.00	90.91	96.15
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf	90.71	95.45	96.77		72.00	93.18	96.15

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.09	87.50	93.55		48.00	84.09	92.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.38	91.85	93.55	74.47	48.00	85.96	94.44

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.86	95.10	88.12	78.08		96.00	97.01	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	88.62	100.00		74.47		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.95	90.91	96.77		60.00	90.91	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	94.07	96.77	95.74	60.00	91.23	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.86	95.10	88.12	78.08		96.00	97.01	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	93.94	100.00		95.74		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.71	95.45	96.77		72.00	93.18	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.14	97.04	96.77	96.81	72.00	92.98	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.86	95.10	88.12	78.08		96.00	97.01	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	94.20	100.00		96.81		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=32808,DigestOffset=56,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
81.09	87.50

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		89	78	87.64
CONT_ASSIGN	137	1	1	100.00
ALWAYS	152	68	57	83.82
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
ALWAYS	441	3	3	100.00
ALWAYS	444	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
152	1	1
155	1	1
158	1	1
159	1	1
162	1	1
163	1	1
164	1	1
167	1	1
170	1	1
171	1	1
172	1	1
174	1	1
179	1	1
181	1	1
182	1	1
184		unreachable
			MISSING_ELSE
193	1	1
194	1	1
195	1	1
			==> MISSING_ELSE
203	1	1
204	1	1
205	1	1
206	1	1
208	1	1
209	0	1
			MISSING_ELSE
212	0	1
213	0	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE
234	1	1
236	1	1
239	1	1
240	1	1
241	1	1
242	1	1
			==> MISSING_ELSE
245	0	1
246	0	1
247	0	1
248	0	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
262	1	1
263	0	1
			MISSING_ELSE
266	0	1
267	0	1
269	0	1
			MISSING_ELSE
278	1	1
279	1	1
			MISSING_ELSE
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
			MISSING_ELSE
304	1	1
305	1	1
306	1	1
307	1	1
			MISSING_ELSE
			MISSING_ELSE
311	1	1
312	1	1
313	1	1
314	1	1
315	1	1
			MISSING_ELSE
			MISSING_ELSE
324	1	1
326	1	1
331	1	1
332	1	1
336	1	1
340	1	1
375	1	1
400	1	1
434	1	1
441	3	3
444	1	1
445	1	1
446	1	1
447	1	1
449	1	1
450	1	1
451	1	1
452	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=67518506,DigestOffset=856,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
90.71	95.45

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		89	85	95.51
CONT_ASSIGN	137	1	1	100.00
ALWAYS	152	68	64	94.12
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
ALWAYS	441	3	3	100.00
ALWAYS	444	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
152	1	1
155	1	1
158	1	1
159	1	1
162	1	1
163	1	1
164	1	1
167	1	1
170	1	1
171	1	1
172	1	1
174	1	1
179	1	1
181	1	1
182	1	1
184		unreachable
			MISSING_ELSE
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
206	1	1
208	1	1
209	1	1
			MISSING_ELSE
212	1	1
213	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE
234	1	1
236	1	1
239	1	1
240	1	1
241	1	1
242	1	1
			==> MISSING_ELSE
245	1	1
246	1	1
247	1	1
248	1	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
262	1	1
263	0	1
			MISSING_ELSE
266	0	1
267	0	1
269	0	1
			MISSING_ELSE
278	1	1
279	1	1
			MISSING_ELSE
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
			MISSING_ELSE
304	1	1
305	1	1
306	1	1
307	1	1
			MISSING_ELSE
			MISSING_ELSE
311	1	1
312	1	1
313	1	1
314	1	1
315	1	1
			MISSING_ELSE
			MISSING_ELSE
324	1	1
326	1	1
331	1	1
332	1	1
336	1	1
340	1	1
375	1	1
400	1	1
434	1	1
441	3	3
444	1	1
445	1	1
446	1	1
447	1	1
449	1	1
450	1	1
451	1	1
452	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=906379306,DigestOffset=1656,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
86.95	90.91

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		89	81	91.01
CONT_ASSIGN	137	1	1	100.00
ALWAYS	152	68	60	88.24
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
ALWAYS	441	3	3	100.00
ALWAYS	444	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
152	1	1
155	1	1
158	1	1
159	1	1
162	1	1
163	1	1
164	1	1
167	1	1
170	1	1
171	1	1
172	1	1
174	1	1
179	1	1
181	1	1
182	1	1
184		unreachable
			MISSING_ELSE
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
206	1	1
208	1	1
209	1	1
			MISSING_ELSE
212	1	1
213	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE
234	1	1
236	1	1
239	1	1
240	1	1
241	1	1
242	1	1
			==> MISSING_ELSE
245	0	1
246	0	1
247	0	1
248	0	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
262	1	1
263	0	1
			MISSING_ELSE
266	0	1
267	0	1
269	0	1
			MISSING_ELSE
278	1	1
279	1	1
			MISSING_ELSE
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
			MISSING_ELSE
304	1	1
305	1	1
306	1	1
307	1	1
			MISSING_ELSE
			MISSING_ELSE
311	1	1
312	1	1
313	1	1
314	1	1
315	1	1
			MISSING_ELSE
			MISSING_ELSE
324	1	1
326	1	1
331	1	1
332	1	1
336	1	1
340	1	1
375	1	1
400	1	1
434	1	1
441	3	3
444	1	1
445	1	1
446	1	1
447	1	1
449	1	1
450	1	1
451	1	1
452	1	1
			MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_part_unbuf

	Total	Covered	Percent
Conditions	31	30	96.77
Logical	31	30	96.77
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T46,T56,T57

 LINE       262
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Not Covered

 LINE       278
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       306
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T52,T53,T54
1	Covered	T52,T53,T54

 LINE       314
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       326
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T9

 LINE       326
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T8
1	1	Covered	T2,T3,T9

 LINE       326
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       331
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T1,T2,T3

 LINE       331
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       340
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T1,T2,T3

 LINE       340
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       375
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       400
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T46,T47

 LINE       400
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T46,T47

---

FSM Coverage for Module : otp_ctrl_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	14	10	71.43
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	212	Covered	T1,T2,T3
IdleSt	184	Covered	T1,T2,T3
InitSt	182	Covered	T1,T2,T3
InitWaitSt	195	Covered	T1,T2,T3
ReadSt	224	Covered	T2,T3,T9
ReadWaitSt	242	Covered	T2,T3,T9
ResetSt	178	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	305	Covered	T1,T2,T3
IdleSt->ReadSt	224	Covered	T2,T3,T9
InitSt->ErrorSt	305	Not Covered
InitSt->InitWaitSt	195	Covered	T1,T2,T3
InitWaitSt->ErrorSt	212	Covered	T46,T73,T74
InitWaitSt->IdleSt	206	Covered	T1,T2,T3
ReadSt->ErrorSt	305	Not Covered
ReadSt->IdleSt	245	Covered	T160
ReadSt->ReadWaitSt	242	Covered	T2,T3,T9
ReadWaitSt->ErrorSt	266	Not Covered
ReadWaitSt->IdleSt	260	Covered	T2,T3,T9
ResetSt->ErrorSt	305	Covered	T52,T53,T54
ResetSt->IdleSt	184	Not Covered
ResetSt->InitSt	182	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	20	8	40.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	246	Covered	T160
CheckFailError	307	Covered	T52,T53,T54
FsmStateError	279	Covered	T1,T2,T3
MacroEccCorrError	209	Covered	T46,T56,T57
NoError	223	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AccessError->CheckFailError	307	Not Covered
AccessError->FsmStateError	315	Covered	T160
AccessError->MacroEccCorrError	209	Not Covered
AccessError->NoError	223	Not Covered
CheckFailError->AccessError	246	Not Covered
CheckFailError->FsmStateError	315	Not Covered
CheckFailError->MacroEccCorrError	209	Not Covered
CheckFailError->NoError	223	Covered	T52,T53,T54
FsmStateError->AccessError	246	Not Covered
FsmStateError->CheckFailError	307	Not Covered
FsmStateError->MacroEccCorrError	209	Not Covered
FsmStateError->NoError	223	Covered	T1,T2,T3
MacroEccCorrError->AccessError	246	Not Covered
MacroEccCorrError->CheckFailError	307	Not Covered
MacroEccCorrError->FsmStateError	315	Covered	T46,T56,T57
MacroEccCorrError->NoError	223	Not Covered
NoError->AccessError	246	Covered	T160
NoError->CheckFailError	307	Covered	T52,T53,T54
NoError->FsmStateError	279	Covered	T1,T2,T3
NoError->MacroEccCorrError	209	Covered	T46,T56,T57

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=32808,DigestOffset=56,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
81.09	84.09

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	37	84.09
TERNARY	326	2	2	100.00
TERNARY	331	2	2	100.00
TERNARY	340	2	2	100.00
TERNARY	375	2	2	100.00
TERNARY	400	2	2	100.00
CASE	174	23	16	69.57
IF	304	3	3	100.00
IF	311	3	3	100.00
IF	441	2	2	100.00
IF	444	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	326	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T17

	LineNo.	Expression
-1-:	340	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T17

	LineNo.	Expression
-1-:	375	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	400	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T47,T73
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	174	case (state_q)
-2-:	179	if (init_req_i)
-3-:	181	if (1'b1)
-4-:	194	if (otp_gnt_i)
-5-:	203	if (otp_rvalid_i)
-6-:	205	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-7-:	208	if ((otp_err_e'(otp_err_i) != NoError))
-8-:	222	if (tlul_req_i)
-9-:	236	if (((({tlul_addr_q, 2'b0} >= 11'b0) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	241	if (otp_gnt_i)
-11-:	257	if (otp_rvalid_i)
-12-:	259	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-13-:	262	if ((otp_err_e'(otp_err_i) != NoError))
-14-:	278	if ((error_q == NoError))
-15-:	283	if (pending_tlul_error_q)
-16-:	286	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T17
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T17
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T17
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T17
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T14,T15,T16
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T9,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T9,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	304	if (ecc_err)
-2-:	306	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T52,T161,T162
1	0	Covered	T52,T161,T162
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	311	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	314	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	441	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	444	if ((!rst_ni))
-2-:	451	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=67518506,DigestOffset=856,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
90.71	93.18

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	41	93.18
TERNARY	326	2	2	100.00
TERNARY	331	2	2	100.00
TERNARY	340	2	2	100.00
TERNARY	375	2	2	100.00
TERNARY	400	2	2	100.00
CASE	174	23	20	86.96
IF	304	3	3	100.00
IF	311	3	3	100.00
IF	441	2	2	100.00
IF	444	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	326	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T9

	LineNo.	Expression
-1-:	340	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T9

	LineNo.	Expression
-1-:	375	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	400	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T146,T48,T73
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	174	case (state_q)
-2-:	179	if (init_req_i)
-3-:	181	if (1'b1)
-4-:	194	if (otp_gnt_i)
-5-:	203	if (otp_rvalid_i)
-6-:	205	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-7-:	208	if ((otp_err_e'(otp_err_i) != NoError))
-8-:	222	if (tlul_req_i)
-9-:	236	if (((({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	241	if (otp_gnt_i)
-11-:	257	if (otp_rvalid_i)
-12-:	259	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-13-:	262	if ((otp_err_e'(otp_err_i) != NoError))
-14-:	278	if ((error_q == NoError))
-15-:	283	if (pending_tlul_error_q)
-16-:	286	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T46,T56,T163
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T73,T74,T164
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T9
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T160
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T14,T15,T16
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T9,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T9,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	304	if (ecc_err)
-2-:	306	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T52,T53,T165
1	0	Covered	T52,T53,T165
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	311	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	314	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	441	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	444	if ((!rst_ni))
-2-:	451	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=906379306,DigestOffset=1656,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
86.95	90.91

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	40	90.91
TERNARY	326	2	2	100.00
TERNARY	331	2	2	100.00
TERNARY	340	2	2	100.00
TERNARY	375	2	2	100.00
TERNARY	400	2	2	100.00
CASE	174	23	19	82.61
IF	304	3	3	100.00
IF	311	3	3	100.00
IF	441	2	2	100.00
IF	444	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	326	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T17

	LineNo.	Expression
-1-:	340	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T17

	LineNo.	Expression
-1-:	375	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	400	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T46,T48,T163
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	174	case (state_q)
-2-:	179	if (init_req_i)
-3-:	181	if (1'b1)
-4-:	194	if (otp_gnt_i)
-5-:	203	if (otp_rvalid_i)
-6-:	205	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-7-:	208	if ((otp_err_e'(otp_err_i) != NoError))
-8-:	222	if (tlul_req_i)
-9-:	236	if (((({tlul_addr_q, 2'b0} >= 11'b01101100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	241	if (otp_gnt_i)
-11-:	257	if (otp_rvalid_i)
-12-:	259	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-13-:	262	if ((otp_err_e'(otp_err_i) != NoError))
-14-:	278	if ((error_q == NoError))
-15-:	283	if (pending_tlul_error_q)
-16-:	286	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T57,T35,T58
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T46,T163,T166
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T17
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T17
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T17
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T17
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T14,T15,T16
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T9,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T9,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	304	if (ecc_err)
-2-:	306	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T52,T54,T165
1	0	Covered	T52,T54,T165
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	311	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	314	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	441	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	444	if ((!rst_ni))
-2-:	451	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	78150048	77420082	0	0
DigestKnown_A	78150048	77420082	0	0
DigestOffsetMustBeRepresentable_A	1656	1656	0	0
EccErrorState_A	78150048	93077	0	0
ErrorKnown_A	78150048	77420082	0	0
FsmStateKnown_A	78150048	77420082	0	0
InitDoneKnown_A	78150048	77420082	0	0
InitReadLocksPartition_A	78150048	11341220	0	0
InitWriteLocksPartition_A	78150048	11341220	0	0
OffsetMustBeBlockAligned_A	1656	1656	0	0
OtpAddrKnown_A	78150048	77420082	0	0
OtpCmdKnown_A	78150048	77420082	0	0
OtpErrorState_A	78150048	86	0	0
OtpReqKnown_A	78150048	77420082	0	0
OtpSizeKnown_A	78150048	77420082	0	0
OtpWdataKnown_A	78150048	77420082	0	0
ReadLockPropagation_A	78150048	549950	0	0
SizeMustBeBlockAligned_A	1656	1656	0	0
TlulGntKnown_A	78150048	77420082	0	0
TlulRdataKnown_A	78150048	77420082	0	0
TlulReadOnReadLock_A	78150048	2720	0	0
TlulRerrorKnown_A	78150048	77420082	0	0
TlulRvalidKnown_A	78150048	77420082	0	0
WriteLockPropagation_A	78150048	0	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	78150048	599419	0	0
u_state_regs_A	78150048	77420082	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1656	1656	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T9	3	3	0	0
T17	3	3	0	0
T18	3	3	0	0
T19	3	3	0	0
T20	3	3	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	93077	0	0
T31	43818	0	0	0
T36	39582	0	0	0
T52	42357	8559	0	0
T53	11550	2124	0	0
T54	9125	2278	0	0
T68	60075	0	0	0
T78	34317	0	0	0
T161	10573	6376	0	0
T162	0	9003	0	0
T165	0	6074	0	0
T167	0	7772	0	0
T168	0	2316	0	0
T169	0	3483	0	0
T170	0	10299	0	0
T171	0	7110	0	0
T172	0	7794	0	0
T173	0	2042	0	0
T174	0	4712	0	0
T175	0	2315	0	0
T176	0	3489	0	0
T177	36924	0	0	0
T178	13671	0	0	0
T179	17190	0	0	0
T180	37923	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	11341220	0	0
T1	44016	28485	0	0
T2	43962	11673	0	0
T3	34809	10488	0	0
T4	74865	3432	0	0
T5	60423	1215	0	0
T9	72882	50559	0	0
T17	56631	17097	0	0
T18	46821	13908	0	0
T19	42153	13998	0	0
T20	36861	15045	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	11341220	0	0
T1	44016	28485	0	0
T2	43962	11673	0	0
T3	34809	10488	0	0
T4	74865	3432	0	0
T5	60423	1215	0	0
T9	72882	50559	0	0
T17	56631	17097	0	0
T18	46821	13908	0	0
T19	42153	13998	0	0
T20	36861	15045	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1656	1656	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T9	3	3	0	0
T17	3	3	0	0
T18	3	3	0	0
T19	3	3	0	0
T20	3	3	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	86	0	0
T6	23159	0	0	0
T7	14644	0	0	0
T8	37926	0	0	0
T12	5513	0	0	0
T13	11176	0	0	0
T21	52684	0	0	0
T29	29315	0	0	0
T46	12885	1	0	0
T47	8968	0	0	0
T56	16500	0	0	0
T57	13926	0	0	0
T64	11876	0	0	0
T65	11992	0	0	0
T66	34514	0	0	0
T73	11067	1	0	0
T74	14153	1	0	0
T98	0	1	0	0
T102	0	1	0	0
T163	21046	1	0	0
T164	0	1	0	0
T166	0	1	0	0
T177	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	64485	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	549950	0	0
T13	11176	4929	0	0
T23	0	11034	0	0
T48	48724	0	0	0
T52	14119	0	0	0
T56	33000	0	0	0
T57	27852	0	0	0
T63	30698	0	0	0
T64	23752	0	0	0
T65	23984	0	0	0
T67	6935	0	0	0
T68	20025	0	0	0
T73	22134	0	0	0
T74	28306	0	0	0
T145	11649	0	0	0
T146	60452	44966	0	0
T150	0	1397	0	0
T151	12342	12427	0	0
T152	0	16971	0	0
T153	0	5742	0	0
T160	0	42722	0	0
T163	21046	0	0	0
T193	20116	14161	0	0
T194	19025	36559	0	0
T195	0	32894	0	0
T196	0	2876	0	0
T197	0	4269	0	0
T198	0	11708	0	0
T199	0	6429	0	0
T200	0	2132	0	0
T201	0	31497	0	0
T202	4062	0	0	0
T203	17193	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1656	1656	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T9	3	3	0	0
T17	3	3	0	0
T18	3	3	0	0
T19	3	3	0	0
T20	3	3	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	2720	0	0
T1	44016	12	0	0
T2	43962	0	0	0
T3	34809	0	0	0
T4	74865	0	0	0
T5	60423	0	0	0
T8	0	33	0	0
T9	72882	19	0	0
T17	56631	0	0	0
T18	46821	0	0	0
T19	42153	0	0	0
T20	36861	0	0	0
T21	0	70	0	0
T48	0	1	0	0
T64	0	1	0	0
T146	0	22	0	0
T151	0	7	0	0
T192	0	58	0	0
T193	0	43	0	0
T203	0	10	0	0
T204	0	14	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	599419	0	0
T5	20141	0	0	0
T6	46318	0	0	0
T7	29288	0	0	0
T8	75852	0	0	0
T11	14160	0	0	0
T12	5513	0	0	0
T13	0	7148	0	0
T20	12287	5117	0	0
T21	105368	0	0	0
T29	58630	0	0	0
T30	0	3721	0	0
T33	11519	0	0	0
T34	0	3605	0	0
T46	25770	3466	0	0
T47	0	3024	0	0
T48	48724	24280	0	0
T56	16500	0	0	0
T57	13926	0	0	0
T58	0	2905	0	0
T63	30698	0	0	0
T64	11876	0	0	0
T65	11992	0	0	0
T73	11067	6635	0	0
T74	14153	6129	0	0
T98	0	2144	0	0
T102	0	3579	0	0
T146	30226	2866	0	0
T163	10523	3693	0	0
T166	0	2465	0	0
T177	0	2828	0	0
T181	0	7263	0	0
T182	0	4465	0	0
T183	0	2375	0	0
T184	0	3808	0	0
T205	0	2882	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	77	87.50
CONT_ASSIGN	137	1	1	100.00
ALWAYS	152	67	56	83.58
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
ALWAYS	441	3	3	100.00
ALWAYS	444	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
152	1	1
155	1	1
158	1	1
159	1	1
162	1	1
163	1	1
164	1	1
167	1	1
170	1	1
171	1	1
172	1	1
174	1	1
179	1	1
181	1	1
182	1	1
184		unreachable
			MISSING_ELSE
193	1	1
194	1	1
195	1	1
			==> MISSING_ELSE
203	1	1
204	1	1
205	1	1
206	1	1
208	1	1
209	0	1
			MISSING_ELSE
212	0	1
213	0	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE
234	1	1
236	1	1
239	1	1
240	1	1
241	1	1
242	1	1
			==> MISSING_ELSE
245	0	1
246	0	1
247	0	1
248	0	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
262	1	1
263	0	1
			MISSING_ELSE
266	0	1
267	0	1
269	0	1
			MISSING_ELSE
278	1	1
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
			MISSING_ELSE
304	1	1
305	1	1
306	1	1
307	1	1
			MISSING_ELSE
			MISSING_ELSE
311	1	1
312	1	1
313	1	1
314	1	1
315	1	1
			MISSING_ELSE
			MISSING_ELSE
324	1	1
326	1	1
331	1	1
332	1	1
336	1	1
340	1	1
375	1	1
400	1	1
434	1	1
441	3	3
444	1	1
445	1	1
446	1	1
447	1	1
449	1	1
450	1	1
451	1	1
452	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	31	29	93.55
Logical	31	29	93.55
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       262
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Not Covered

 LINE       278
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       306
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T52,T161,T162
1	Covered	T52,T161,T162

 LINE       314
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       326
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       326
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T8
1	1	Covered	T2,T3,T17

 LINE       326
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       331
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T1,T2,T3

 LINE       331
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       340
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T1,T2,T3

 LINE       340
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       375
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       400
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T47,T73

 LINE       400
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T47,T73

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	14	8	57.14
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	212	Covered	T1,T2,T3
IdleSt	184	Covered	T1,T2,T3
InitSt	182	Covered	T1,T2,T3
InitWaitSt	195	Covered	T1,T2,T3
ReadSt	224	Covered	T2,T3,T17
ReadWaitSt	242	Covered	T2,T3,T17
ResetSt	178	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	305	Covered	T1,T2,T3
IdleSt->ReadSt	224	Covered	T2,T3,T17
InitSt->ErrorSt	305	Not Covered
InitSt->InitWaitSt	195	Covered	T1,T2,T3
InitWaitSt->ErrorSt	212	Not Covered
InitWaitSt->IdleSt	206	Covered	T1,T2,T3
ReadSt->ErrorSt	305	Not Covered
ReadSt->IdleSt	245	Not Covered
ReadSt->ReadWaitSt	242	Covered	T2,T3,T17
ReadWaitSt->ErrorSt	266	Not Covered
ReadWaitSt->IdleSt	260	Covered	T2,T3,T17
ResetSt->ErrorSt	305	Covered	T52,T53,T54
ResetSt->IdleSt	184	Not Covered
ResetSt->InitSt	182	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	3	60.00	(Not included in score)
Transitions	11	4	36.36
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	246	Not Covered
CheckFailError	307	Covered	T52,T161,T162
FsmStateError	279	Covered	T1,T2,T3
MacroEccCorrError	209	Not Covered
NoError	223	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	307	Excluded		VC_COV_UNR
AccessError->FsmStateError	315	Not Covered
AccessError->MacroEccCorrError	209	Excluded		VC_COV_UNR
AccessError->NoError	223	Not Covered
CheckFailError->AccessError	246	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	315	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	209	Excluded		VC_COV_UNR
CheckFailError->NoError	223	Covered	T52,T161,T162
FsmStateError->AccessError	246	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	307	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	209	Excluded		VC_COV_UNR
FsmStateError->NoError	223	Covered	T1,T2,T3
MacroEccCorrError->AccessError	246	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	307	Not Covered
MacroEccCorrError->FsmStateError	315	Not Covered
MacroEccCorrError->NoError	223	Not Covered
NoError->AccessError	246	Not Covered
NoError->CheckFailError	307	Covered	T52,T161,T162
NoError->FsmStateError	279	Covered	T1,T2,T3
NoError->MacroEccCorrError	209	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	37	84.09
TERNARY	326	2	2	100.00
TERNARY	331	2	2	100.00
TERNARY	340	2	2	100.00
TERNARY	375	2	2	100.00
TERNARY	400	2	2	100.00
CASE	174	23	16	69.57
IF	304	3	3	100.00
IF	311	3	3	100.00
IF	441	2	2	100.00
IF	444	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	326	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T17

	LineNo.	Expression
-1-:	340	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T17

	LineNo.	Expression
-1-:	375	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	400	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T47,T73
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	174	case (state_q)
-2-:	179	if (init_req_i)
-3-:	181	if (1'b1)
-4-:	194	if (otp_gnt_i)
-5-:	203	if (otp_rvalid_i)
-6-:	205	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-7-:	208	if ((otp_err_e'(otp_err_i) != NoError))
-8-:	222	if (tlul_req_i)
-9-:	236	if (((({tlul_addr_q, 2'b0} >= 11'b0) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	241	if (otp_gnt_i)
-11-:	257	if (otp_rvalid_i)
-12-:	259	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-13-:	262	if ((otp_err_e'(otp_err_i) != NoError))
-14-:	278	if ((error_q == NoError))
-15-:	283	if (pending_tlul_error_q)
-16-:	286	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T17
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T17
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T17
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T17
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T14,T15,T16
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T9,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T9,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	304	if (ecc_err)
-2-:	306	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T52,T161,T162
1	0	Covered	T52,T161,T162
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	311	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	314	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	441	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	444	if ((!rst_ni))
-2-:	451	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	24	92.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	24	92.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	26050016	25806694	0	0
DigestKnown_A	26050016	25806694	0	0
DigestOffsetMustBeRepresentable_A	552	552	0	0
EccErrorState_A	26050016	24259	0	0
ErrorKnown_A	26050016	25806694	0	0
FsmStateKnown_A	26050016	25806694	0	0
InitDoneKnown_A	26050016	25806694	0	0
InitReadLocksPartition_A	26050016	3730231	0	0
InitWriteLocksPartition_A	26050016	3730231	0	0
OffsetMustBeBlockAligned_A	552	552	0	0
OtpAddrKnown_A	26050016	25806694	0	0
OtpCmdKnown_A	26050016	25806694	0	0
OtpErrorState_A	26050016	0	0	0
OtpReqKnown_A	26050016	25806694	0	0
OtpSizeKnown_A	26050016	25806694	0	0
OtpWdataKnown_A	26050016	25806694	0	0
ReadLockPropagation_A	26050016	184508	0	0
SizeMustBeBlockAligned_A	552	552	0	0
TlulGntKnown_A	26050016	25806694	0	0
TlulRdataKnown_A	26050016	25806694	0	0
TlulReadOnReadLock_A	26050016	725	0	0
TlulRerrorKnown_A	26050016	25806694	0	0
TlulRvalidKnown_A	26050016	25806694	0	0
WriteLockPropagation_A	26050016	0	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	26050016	308472	0	0
u_state_regs_A	26050016	25806694	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	24259	0	0
T31	14606	0	0	0
T36	13194	0	0	0
T52	14119	2853	0	0
T68	20025	0	0	0
T78	11439	0	0	0
T161	10573	3188	0	0
T162	0	3001	0	0
T170	0	3433	0	0
T172	0	3897	0	0
T173	0	2042	0	0
T174	0	2356	0	0
T176	0	3489	0	0
T177	12308	0	0	0
T178	4557	0	0	0
T179	5730	0	0	0
T180	12641	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	3730231	0	0
T1	14672	9461	0	0
T2	14654	3857	0	0
T3	11603	3445	0	0
T4	24955	1025	0	0
T5	20141	320	0	0
T9	24294	16802	0	0
T17	18877	5648	0	0
T18	15607	4602	0	0
T19	14051	4632	0	0
T20	12287	4981	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	3730231	0	0
T1	14672	9461	0	0
T2	14654	3857	0	0
T3	11603	3445	0	0
T4	24955	1025	0	0
T5	20141	320	0	0
T9	24294	16802	0	0
T17	18877	5648	0	0
T18	15607	4602	0	0
T19	14051	4632	0	0
T20	12287	4981	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	184508	0	0
T13	0	1661	0	0
T23	0	11034	0	0
T48	24362	0	0	0
T56	16500	0	0	0
T57	13926	0	0	0
T63	15349	0	0	0
T64	11876	0	0	0
T65	11992	0	0	0
T73	11067	0	0	0
T74	14153	0	0	0
T146	30226	22295	0	0
T150	0	589	0	0
T151	0	6220	0	0
T152	0	8597	0	0
T163	10523	0	0	0
T194	0	12155	0	0
T195	0	16451	0	0
T196	0	1438	0	0
T198	0	11708	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	725	0	0
T1	14672	2	0	0
T2	14654	0	0	0
T3	11603	0	0	0
T4	24955	0	0	0
T5	20141	0	0	0
T8	0	15	0	0
T9	24294	5	0	0
T17	18877	0	0	0
T18	15607	0	0	0
T19	14051	0	0	0
T20	12287	0	0	0
T21	0	22	0	0
T48	0	1	0	0
T64	0	1	0	0
T146	0	7	0	0
T192	0	15	0	0
T203	0	3	0	0
T204	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	308472	0	0
T5	20141	0	0	0
T6	23159	0	0	0
T7	14644	0	0	0
T8	37926	0	0	0
T11	14160	0	0	0
T20	12287	5117	0	0
T21	52684	0	0	0
T29	29315	0	0	0
T30	0	3721	0	0
T33	11519	0	0	0
T34	0	3605	0	0
T46	12885	0	0	0
T47	0	3024	0	0
T58	0	2905	0	0
T73	0	3320	0	0
T74	0	3067	0	0
T181	0	3634	0	0
T182	0	2235	0	0
T205	0	2882	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	80	90.91
CONT_ASSIGN	137	1	1	100.00
ALWAYS	152	67	59	88.06
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
ALWAYS	441	3	3	100.00
ALWAYS	444	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
152	1	1
155	1	1
158	1	1
159	1	1
162	1	1
163	1	1
164	1	1
167	1	1
170	1	1
171	1	1
172	1	1
174	1	1
179	1	1
181	1	1
182	1	1
184		unreachable
			MISSING_ELSE
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
206	1	1
208	1	1
209	1	1
			MISSING_ELSE
212	1	1
213	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE
234	1	1
236	1	1
239	1	1
240	1	1
241	1	1
242	1	1
			==> MISSING_ELSE
245	0	1
246	0	1
247	0	1
248	0	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
262	1	1
263	0	1
			MISSING_ELSE
266	0	1
267	0	1
269	0	1
			MISSING_ELSE
278	1	1
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
			MISSING_ELSE
304	1	1
305	1	1
306	1	1
307	1	1
			MISSING_ELSE
			MISSING_ELSE
311	1	1
312	1	1
313	1	1
314	1	1
315	1	1
			MISSING_ELSE
			MISSING_ELSE
324	1	1
326	1	1
331	1	1
332	1	1
336	1	1
340	1	1
375	1	1
400	1	1
434	1	1
441	3	3
444	1	1
445	1	1
446	1	1
447	1	1
449	1	1
450	1	1
451	1	1
452	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	31	30	96.77
Logical	31	30	96.77
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T57,T35,T58

 LINE       262
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Not Covered

 LINE       278
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       306
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T52,T54,T165
1	Covered	T52,T54,T165

 LINE       314
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       326
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       326
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T8
1	1	Covered	T2,T3,T17

 LINE       326
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       331
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T1,T2,T3

 LINE       331
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       340
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T1,T2,T3

 LINE       340
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       375
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       400
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T46,T48,T163

 LINE       400
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T46,T48,T163

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	14	9	64.29
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	212	Covered	T1,T2,T3
IdleSt	184	Covered	T1,T2,T3
InitSt	182	Covered	T1,T2,T3
InitWaitSt	195	Covered	T1,T2,T3
ReadSt	224	Covered	T2,T3,T17
ReadWaitSt	242	Covered	T2,T3,T17
ResetSt	178	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	305	Covered	T1,T2,T3
IdleSt->ReadSt	224	Covered	T2,T3,T17
InitSt->ErrorSt	305	Not Covered
InitSt->InitWaitSt	195	Covered	T1,T2,T3
InitWaitSt->ErrorSt	212	Covered	T46,T73,T74
InitWaitSt->IdleSt	206	Covered	T1,T2,T3
ReadSt->ErrorSt	305	Not Covered
ReadSt->IdleSt	245	Not Covered
ReadSt->ReadWaitSt	242	Covered	T2,T3,T17
ReadWaitSt->ErrorSt	266	Not Covered
ReadWaitSt->IdleSt	260	Covered	T2,T3,T17
ResetSt->ErrorSt	305	Covered	T52,T53,T54
ResetSt->IdleSt	184	Not Covered
ResetSt->InitSt	182	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	11	6	54.55
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	246	Not Covered
CheckFailError	307	Covered	T52,T54,T165
FsmStateError	279	Covered	T1,T2,T3
MacroEccCorrError	209	Covered	T57,T35,T58
NoError	223	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	307	Excluded		VC_COV_UNR
AccessError->FsmStateError	315	Not Covered
AccessError->MacroEccCorrError	209	Excluded		VC_COV_UNR
AccessError->NoError	223	Not Covered
CheckFailError->AccessError	246	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	315	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	209	Excluded		VC_COV_UNR
CheckFailError->NoError	223	Covered	T52,T54,T165
FsmStateError->AccessError	246	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	307	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	209	Excluded		VC_COV_UNR
FsmStateError->NoError	223	Covered	T1,T2,T3
MacroEccCorrError->AccessError	246	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	307	Not Covered
MacroEccCorrError->FsmStateError	315	Covered	T57,T35,T58
MacroEccCorrError->NoError	223	Not Covered
NoError->AccessError	246	Not Covered
NoError->CheckFailError	307	Covered	T52,T54,T165
NoError->FsmStateError	279	Covered	T1,T2,T3
NoError->MacroEccCorrError	209	Covered	T57,T35,T58

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	40	90.91
TERNARY	326	2	2	100.00
TERNARY	331	2	2	100.00
TERNARY	340	2	2	100.00
TERNARY	375	2	2	100.00
TERNARY	400	2	2	100.00
CASE	174	23	19	82.61
IF	304	3	3	100.00
IF	311	3	3	100.00
IF	441	2	2	100.00
IF	444	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	326	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T17

	LineNo.	Expression
-1-:	340	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T17

	LineNo.	Expression
-1-:	375	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	400	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T46,T48,T163
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	174	case (state_q)
-2-:	179	if (init_req_i)
-3-:	181	if (1'b1)
-4-:	194	if (otp_gnt_i)
-5-:	203	if (otp_rvalid_i)
-6-:	205	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-7-:	208	if ((otp_err_e'(otp_err_i) != NoError))
-8-:	222	if (tlul_req_i)
-9-:	236	if (((({tlul_addr_q, 2'b0} >= 11'b01101100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	241	if (otp_gnt_i)
-11-:	257	if (otp_rvalid_i)
-12-:	259	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-13-:	262	if ((otp_err_e'(otp_err_i) != NoError))
-14-:	278	if ((error_q == NoError))
-15-:	283	if (pending_tlul_error_q)
-16-:	286	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T57,T35,T58
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T46,T163,T166
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T17
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T17
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T17
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T17
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T14,T15,T16
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T9,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T9,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	304	if (ecc_err)
-2-:	306	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T52,T54,T165
1	0	Covered	T52,T54,T165
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	311	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	314	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	441	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	444	if ((!rst_ni))
-2-:	451	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	26050016	25806694	0	0
DigestKnown_A	26050016	25806694	0	0
DigestOffsetMustBeRepresentable_A	552	552	0	0
EccErrorState_A	26050016	37943	0	0
ErrorKnown_A	26050016	25806694	0	0
FsmStateKnown_A	26050016	25806694	0	0
InitDoneKnown_A	26050016	25806694	0	0
InitReadLocksPartition_A	26050016	3830323	0	0
InitWriteLocksPartition_A	26050016	3830323	0	0
OffsetMustBeBlockAligned_A	552	552	0	0
OtpAddrKnown_A	26050016	25806694	0	0
OtpCmdKnown_A	26050016	25806694	0	0
OtpErrorState_A	26050016	37	0	0
OtpReqKnown_A	26050016	25806694	0	0
OtpSizeKnown_A	26050016	25806694	0	0
OtpWdataKnown_A	26050016	25806694	0	0
ReadLockPropagation_A	26050016	223236	0	0
SizeMustBeBlockAligned_A	552	552	0	0
TlulGntKnown_A	26050016	25806694	0	0
TlulRdataKnown_A	26050016	25806694	0	0
TlulReadOnReadLock_A	26050016	979	0	0
TlulRerrorKnown_A	26050016	25806694	0	0
TlulRvalidKnown_A	26050016	25806694	0	0
WriteLockPropagation_A	26050016	0	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	26050016	123902	0	0
u_state_regs_A	26050016	25806694	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	37943	0	0
T31	14606	0	0	0
T36	13194	0	0	0
T52	14119	2853	0	0
T54	9125	2278	0	0
T68	20025	0	0	0
T78	11439	0	0	0
T162	0	3001	0	0
T165	0	3037	0	0
T167	0	3886	0	0
T168	0	2316	0	0
T170	0	3433	0	0
T171	0	3555	0	0
T172	0	3897	0	0
T174	0	2356	0	0
T177	12308	0	0	0
T178	4557	0	0	0
T179	5730	0	0	0
T180	12641	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	3830323	0	0
T1	14672	9529	0	0
T2	14654	3925	0	0
T3	11603	3547	0	0
T4	24955	1263	0	0
T5	20141	490	0	0
T9	24294	16904	0	0
T17	18877	5750	0	0
T18	15607	4670	0	0
T19	14051	4700	0	0
T20	12287	5049	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	3830323	0	0
T1	14672	9529	0	0
T2	14654	3925	0	0
T3	11603	3547	0	0
T4	24955	1263	0	0
T5	20141	490	0	0
T9	24294	16904	0	0
T17	18877	5750	0	0
T18	15607	4670	0	0
T19	14051	4700	0	0
T20	12287	5049	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	37	0	0
T6	23159	0	0	0
T7	14644	0	0	0
T8	37926	0	0	0
T12	5513	0	0	0
T21	52684	0	0	0
T29	29315	0	0	0
T46	12885	1	0	0
T47	8968	0	0	0
T66	17257	0	0	0
T98	0	1	0	0
T102	0	1	0	0
T163	10523	1	0	0
T166	0	1	0	0
T185	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	223236	0	0
T13	0	1633	0	0
T48	24362	0	0	0
T56	16500	0	0	0
T57	13926	0	0	0
T63	15349	0	0	0
T64	11876	0	0	0
T65	11992	0	0	0
T73	11067	0	0	0
T74	14153	0	0	0
T146	30226	22671	0	0
T150	0	403	0	0
T153	0	5742	0	0
T160	0	21359	0	0
T163	10523	0	0	0
T193	0	14161	0	0
T194	0	12255	0	0
T195	0	16443	0	0
T196	0	1438	0	0
T199	0	3227	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	979	0	0
T1	14672	6	0	0
T2	14654	0	0	0
T3	11603	0	0	0
T4	24955	0	0	0
T5	20141	0	0	0
T8	0	10	0	0
T9	24294	10	0	0
T17	18877	0	0	0
T18	15607	0	0	0
T19	14051	0	0	0
T20	12287	0	0	0
T21	0	23	0	0
T146	0	8	0	0
T151	0	5	0	0
T192	0	16	0	0
T193	0	19	0	0
T203	0	5	0	0
T204	0	4	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	123902	0	0
T6	23159	0	0	0
T7	14644	0	0	0
T8	37926	0	0	0
T12	5513	0	0	0
T13	0	3557	0	0
T21	52684	0	0	0
T29	29315	0	0	0
T46	12885	3466	0	0
T47	8968	0	0	0
T48	24362	12106	0	0
T63	15349	0	0	0
T98	0	2144	0	0
T102	0	3579	0	0
T163	0	3693	0	0
T166	0	2465	0	0
T185	0	3650	0	0
T188	0	3502	0	0
T189	0	3314	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	84	95.45
CONT_ASSIGN	137	1	1	100.00
ALWAYS	152	67	63	94.03
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
ALWAYS	441	3	3	100.00
ALWAYS	444	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
152	1	1
155	1	1
158	1	1
159	1	1
162	1	1
163	1	1
164	1	1
167	1	1
170	1	1
171	1	1
172	1	1
174	1	1
179	1	1
181	1	1
182	1	1
184		unreachable
			MISSING_ELSE
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
206	1	1
208	1	1
209	1	1
			MISSING_ELSE
212	1	1
213	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE
234	1	1
236	1	1
239	1	1
240	1	1
241	1	1
242	1	1
			==> MISSING_ELSE
245	1	1
246	1	1
247	1	1
248	1	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
262	1	1
263	0	1
			MISSING_ELSE
266	0	1
267	0	1
269	0	1
			MISSING_ELSE
278	1	1
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
			MISSING_ELSE
304	1	1
305	1	1
306	1	1
307	1	1
			MISSING_ELSE
			MISSING_ELSE
311	1	1
312	1	1
313	1	1
314	1	1
315	1	1
			MISSING_ELSE
			MISSING_ELSE
324	1	1
326	1	1
331	1	1
332	1	1
336	1	1
340	1	1
375	1	1
400	1	1
434	1	1
441	3	3
444	1	1
445	1	1
446	1	1
447	1	1
449	1	1
450	1	1
451	1	1
452	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	31	30	96.77
Logical	31	30	96.77
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T46,T56,T163

 LINE       262
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Not Covered

 LINE       278
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       306
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T52,T53,T165
1	Covered	T52,T53,T165

 LINE       314
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       326
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T9

 LINE       326
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T8
1	1	Covered	T2,T3,T9

 LINE       326
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       331
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T1,T2,T3

 LINE       331
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       340
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T9
1	Covered	T1,T2,T3

 LINE       340
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       375
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       400
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T146,T48,T73

 LINE       400
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T146,T48,T73

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	14	10	71.43
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	212	Covered	T1,T2,T3
IdleSt	184	Covered	T1,T2,T3
InitSt	182	Covered	T1,T2,T3
InitWaitSt	195	Covered	T1,T2,T3
ReadSt	224	Covered	T2,T3,T9
ReadWaitSt	242	Covered	T2,T3,T9
ResetSt	178	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	305	Covered	T1,T2,T3
IdleSt->ReadSt	224	Covered	T2,T3,T9
InitSt->ErrorSt	305	Not Covered
InitSt->InitWaitSt	195	Covered	T1,T2,T3
InitWaitSt->ErrorSt	212	Covered	T73,T74,T164
InitWaitSt->IdleSt	206	Covered	T1,T2,T3
ReadSt->ErrorSt	305	Not Covered
ReadSt->IdleSt	245	Covered	T160
ReadSt->ReadWaitSt	242	Covered	T2,T3,T9
ReadWaitSt->ErrorSt	266	Not Covered
ReadWaitSt->IdleSt	260	Covered	T2,T3,T9
ResetSt->ErrorSt	305	Covered	T52,T53,T54
ResetSt->IdleSt	184	Not Covered
ResetSt->InitSt	182	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	8	72.73
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	246	Covered	T160
CheckFailError	307	Covered	T52,T53,T165
FsmStateError	279	Covered	T1,T2,T3
MacroEccCorrError	209	Covered	T46,T56,T163
NoError	223	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	307	Excluded		VC_COV_UNR
AccessError->FsmStateError	315	Covered	T160
AccessError->MacroEccCorrError	209	Excluded		VC_COV_UNR
AccessError->NoError	223	Not Covered
CheckFailError->AccessError	246	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	315	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	209	Excluded		VC_COV_UNR
CheckFailError->NoError	223	Covered	T52,T53,T165
FsmStateError->AccessError	246	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	307	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	209	Excluded		VC_COV_UNR
FsmStateError->NoError	223	Covered	T1,T2,T3
MacroEccCorrError->AccessError	246	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	307	Not Covered
MacroEccCorrError->FsmStateError	315	Covered	T46,T56,T163
MacroEccCorrError->NoError	223	Not Covered
NoError->AccessError	246	Covered	T160
NoError->CheckFailError	307	Covered	T52,T53,T165
NoError->FsmStateError	279	Covered	T1,T2,T3
NoError->MacroEccCorrError	209	Covered	T46,T56,T163

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	41	93.18
TERNARY	326	2	2	100.00
TERNARY	331	2	2	100.00
TERNARY	340	2	2	100.00
TERNARY	375	2	2	100.00
TERNARY	400	2	2	100.00
CASE	174	23	20	86.96
IF	304	3	3	100.00
IF	311	3	3	100.00
IF	441	2	2	100.00
IF	444	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	326	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T9

	LineNo.	Expression
-1-:	340	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T9

	LineNo.	Expression
-1-:	375	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	400	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T146,T48,T73
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	174	case (state_q)
-2-:	179	if (init_req_i)
-3-:	181	if (1'b1)
-4-:	194	if (otp_gnt_i)
-5-:	203	if (otp_rvalid_i)
-6-:	205	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-7-:	208	if ((otp_err_e'(otp_err_i) != NoError))
-8-:	222	if (tlul_req_i)
-9-:	236	if (((({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	241	if (otp_gnt_i)
-11-:	257	if (otp_rvalid_i)
-12-:	259	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-13-:	262	if ((otp_err_e'(otp_err_i) != NoError))
-14-:	278	if ((error_q == NoError))
-15-:	283	if (pending_tlul_error_q)
-16-:	286	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T46,T56,T163
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T73,T74,T164
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T9
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T160
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T14,T15,T16
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T9,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T9,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	304	if (ecc_err)
-2-:	306	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T52,T53,T165
1	0	Covered	T52,T53,T165
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	311	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	314	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	441	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	444	if ((!rst_ni))
-2-:	451	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	26050016	25806694	0	0
DigestKnown_A	26050016	25806694	0	0
DigestOffsetMustBeRepresentable_A	552	552	0	0
EccErrorState_A	26050016	30875	0	0
ErrorKnown_A	26050016	25806694	0	0
FsmStateKnown_A	26050016	25806694	0	0
InitDoneKnown_A	26050016	25806694	0	0
InitReadLocksPartition_A	26050016	3780666	0	0
InitWriteLocksPartition_A	26050016	3780666	0	0
OffsetMustBeBlockAligned_A	552	552	0	0
OtpAddrKnown_A	26050016	25806694	0	0
OtpCmdKnown_A	26050016	25806694	0	0
OtpErrorState_A	26050016	49	0	0
OtpReqKnown_A	26050016	25806694	0	0
OtpSizeKnown_A	26050016	25806694	0	0
OtpWdataKnown_A	26050016	25806694	0	0
ReadLockPropagation_A	26050016	142206	0	0
SizeMustBeBlockAligned_A	552	552	0	0
TlulGntKnown_A	26050016	25806694	0	0
TlulRdataKnown_A	26050016	25806694	0	0
TlulReadOnReadLock_A	26050016	1016	0	0
TlulRerrorKnown_A	26050016	25806694	0	0
TlulRvalidKnown_A	26050016	25806694	0	0
WriteLockPropagation_A	26050016	0	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	26050016	167045	0	0
u_state_regs_A	26050016	25806694	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	30875	0	0
T31	14606	0	0	0
T36	13194	0	0	0
T52	14119	2853	0	0
T53	11550	2124	0	0
T68	20025	0	0	0
T78	11439	0	0	0
T161	0	3188	0	0
T162	0	3001	0	0
T165	0	3037	0	0
T167	0	3886	0	0
T169	0	3483	0	0
T170	0	3433	0	0
T171	0	3555	0	0
T175	0	2315	0	0
T177	12308	0	0	0
T178	4557	0	0	0
T179	5730	0	0	0
T180	12641	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	3780666	0	0
T1	14672	9495	0	0
T2	14654	3891	0	0
T3	11603	3496	0	0
T4	24955	1144	0	0
T5	20141	405	0	0
T9	24294	16853	0	0
T17	18877	5699	0	0
T18	15607	4636	0	0
T19	14051	4666	0	0
T20	12287	5015	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	3780666	0	0
T1	14672	9495	0	0
T2	14654	3891	0	0
T3	11603	3496	0	0
T4	24955	1144	0	0
T5	20141	405	0	0
T9	24294	16853	0	0
T17	18877	5699	0	0
T18	15607	4636	0	0
T19	14051	4666	0	0
T20	12287	5015	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	49	0	0
T13	11176	0	0	0
T56	16500	0	0	0
T57	13926	0	0	0
T64	11876	0	0	0
T65	11992	0	0	0
T66	17257	0	0	0
T73	11067	1	0	0
T74	14153	1	0	0
T163	10523	0	0	0
T164	0	1	0	0
T177	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T192	64485	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	142206	0	0
T13	11176	1635	0	0
T52	14119	0	0	0
T67	6935	0	0	0
T68	20025	0	0	0
T145	11649	0	0	0
T150	0	405	0	0
T151	12342	6207	0	0
T152	0	8374	0	0
T160	0	21363	0	0
T193	20116	0	0	0
T194	19025	12149	0	0
T197	0	4269	0	0
T199	0	3202	0	0
T200	0	2132	0	0
T201	0	31497	0	0
T202	4062	0	0	0
T203	17193	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	1016	0	0
T1	14672	4	0	0
T2	14654	0	0	0
T3	11603	0	0	0
T4	24955	0	0	0
T5	20141	0	0	0
T8	0	8	0	0
T9	24294	4	0	0
T17	18877	0	0	0
T18	15607	0	0	0
T19	14051	0	0	0
T20	12287	0	0	0
T21	0	25	0	0
T146	0	7	0	0
T151	0	2	0	0
T192	0	27	0	0
T193	0	24	0	0
T203	0	2	0	0
T204	0	8	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	167045	0	0
T13	0	3591	0	0
T48	24362	12174	0	0
T56	16500	0	0	0
T57	13926	0	0	0
T63	15349	0	0	0
T64	11876	0	0	0
T65	11992	0	0	0
T73	11067	3315	0	0
T74	14153	3062	0	0
T146	30226	2866	0	0
T163	10523	0	0	0
T177	0	2828	0	0
T181	0	3629	0	0
T182	0	2230	0	0
T183	0	2375	0	0
T184	0	3808	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0