Unified Coverage Report :: Module :: prim_sparse_fsm_flop

Module : prim_sparse_fsm_flop

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs	0.00	0.00
tb.dut.u_tlul_lc_gate.u_state_regs	0.00	0.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_state_regs	0.00	0.00
tb.dut.u_otp_ctrl_scrmbl.u_state_regs	0.00	0.00
tb.dut.u_otp_ctrl_dai.u_state_regs	0.00	0.00
tb.dut.u_otp_ctrl_lci.u_state_regs	0.00	0.00
tb.dut.u_otp_ctrl_kdi.u_state_regs	0.00	0.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_state_regs	0.00	0.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_state_regs	0.00	0.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_state_regs	0.00	0.00
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_state_regs	0.00	0.00
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_state_regs	0.00	0.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_state_regs	0.00	0.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_state_regs	0.00	0.00
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_state_regs	0.00	0.00

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_otp_ctrl_lfsr_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_tlul_lc_gate.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_tlul_lc_gate

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_otp_ctrl_scrmbl.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_otp_ctrl_scrmbl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_otp_ctrl_dai.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_otp_ctrl_dai

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_otp_ctrl_lci.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_otp_ctrl_lci

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_otp_ctrl_kdi.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_otp_ctrl_kdi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[0].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[1].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[2].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[3].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[4].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[7].gen_lifecycle.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

Line Coverage for Module : prim_sparse_fsm_flop

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.u_otp_ctrl_dai.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.u_otp_ctrl_lci.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.u_otp_ctrl_kdi.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1