Unified Coverage Report :: Module :: otp_ctrl_part_unbuf

Module : otp_ctrl_part_unbuf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf	0.00	0.00	0.00		0.00	0.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf	0.00	0.00	0.00		0.00	0.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
6.75	0.00	0.00	27.01		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	0.00	0.00				0.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	0.00	0.00		0.00		0.00
u_prim_mubi8_sender_read_lock_pre	0.00	0.00				0.00
u_prim_mubi8_sender_write_lock_pre	0.00	0.00				0.00
u_state_regs	0.00	0.00				0.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
6.75	0.00	0.00	27.01		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	0.00	0.00				0.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	0.00	0.00		0.00		0.00
u_prim_mubi8_sender_read_lock_pre	0.00	0.00				0.00
u_prim_mubi8_sender_write_lock_pre	0.00	0.00				0.00
u_state_regs	0.00	0.00				0.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
6.75	0.00	0.00	27.01		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	0.00	0.00				0.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	0.00	0.00		0.00		0.00
u_prim_mubi8_sender_read_lock_pre	0.00	0.00				0.00
u_prim_mubi8_sender_write_lock_pre	0.00	0.00				0.00
u_state_regs	0.00	0.00				0.00

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		90	0	0.00
CONT_ASSIGN	138	1	0	0.00
ALWAYS	153	68	0	0.00
CONT_ASSIGN	323	1	0	0.00
CONT_ASSIGN	325	1	0	0.00
CONT_ASSIGN	328	1	0	0.00
CONT_ASSIGN	338	1	0	0.00
CONT_ASSIGN	339	1	0	0.00
CONT_ASSIGN	343	1	0	0.00
CONT_ASSIGN	347	1	0	0.00
CONT_ASSIGN	384	1	0	0.00
CONT_ASSIGN	409	1	0	0.00
CONT_ASSIGN	443	1	0	0.00
ALWAYS	450	3	0	0.00
ALWAYS	453	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	0	1
153	0	1
156	0	1
159	0	1
160	0	1
163	0	1
164	0	1
165	0	1
168	0	1
171	0	1
172	0	1
173	0	1
175	0	1
180	0	1
182	0	1
183	0	1
185		unreachable
			==> MISSING_ELSE
194	0	1
195	0	1
196	0	1
			==> MISSING_ELSE
204	0	1
205	0	1
206	0	1
207	0	1
209	0	1
210	0	1
			==> MISSING_ELSE
213	0	1
214	0	1
			==> MISSING_ELSE
222	0	1
223	0	1
224	0	1
225	0	1
226	0	1
			==> MISSING_ELSE
235	0	1
237	0	1
238	0	1
239	0	1
240	0	1
241	0	1
			==> MISSING_ELSE
244	0	1
245	0	1
246	0	1
247	0	1
255	0	1
256	0	1
257	0	1
258	0	1
259	0	1
261	0	1
262	0	1
			==> MISSING_ELSE
265	0	1
266	0	1
268	0	1
			==> MISSING_ELSE
277	0	1
278	0	1
			==> MISSING_ELSE
282	0	1
283	0	1
284	0	1
285	0	1
286	0	1
287	0	1
			==> MISSING_ELSE
303	0	1
304	0	1
305	0	1
306	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
310	0	1
311	0	1
312	0	1
313	0	1
314	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
323	0	1
325	0	1
328	0	1
338	0	1
339	0	1
343	0	1
347	0	1
384	0	1
409	0	1
443	0	1
450	0	3
453	0	1
454	0	1
455	0	1
456	0	1
458	0	1
459	0	1
460	0	1
461	0	1
			==> MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=135037012,DigestOffset=856,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		90	0	0.00
CONT_ASSIGN	138	1	0	0.00
ALWAYS	153	68	0	0.00
CONT_ASSIGN	323	1	0	0.00
CONT_ASSIGN	325	1	0	0.00
CONT_ASSIGN	331	1	0	0.00
CONT_ASSIGN	338	1	0	0.00
CONT_ASSIGN	339	1	0	0.00
CONT_ASSIGN	343	1	0	0.00
CONT_ASSIGN	347	1	0	0.00
CONT_ASSIGN	384	1	0	0.00
CONT_ASSIGN	409	1	0	0.00
CONT_ASSIGN	443	1	0	0.00
ALWAYS	450	3	0	0.00
ALWAYS	453	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	0	1
153	0	1
156	0	1
159	0	1
160	0	1
163	0	1
164	0	1
165	0	1
168	0	1
171	0	1
172	0	1
173	0	1
175	0	1
180	0	1
182	0	1
183	0	1
185		unreachable
			==> MISSING_ELSE
194	0	1
195	0	1
196	0	1
			==> MISSING_ELSE
204	0	1
205	0	1
206	0	1
207	0	1
209	0	1
210	0	1
			==> MISSING_ELSE
213	0	1
214	0	1
			==> MISSING_ELSE
222	0	1
223	0	1
224	0	1
225	0	1
226	0	1
			==> MISSING_ELSE
235	0	1
237	0	1
238	0	1
239	0	1
240	0	1
241	0	1
			==> MISSING_ELSE
244	0	1
245	0	1
246	0	1
247	0	1
255	0	1
256	0	1
257	0	1
258	0	1
259	0	1
261	0	1
262	0	1
			==> MISSING_ELSE
265	0	1
266	0	1
268	0	1
			==> MISSING_ELSE
277	0	1
278	0	1
			==> MISSING_ELSE
282	0	1
283	0	1
284	0	1
285	0	1
286	0	1
287	0	1
			==> MISSING_ELSE
303	0	1
304	0	1
305	0	1
306	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
310	0	1
311	0	1
312	0	1
313	0	1
314	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
323	0	1
325	0	1
331	0	1
338	0	1
339	0	1
343	0	1
347	0	1
384	0	1
409	0	1
443	0	1
450	0	3
453	0	1
454	0	1
455	0	1
456	0	1
458	0	1
459	0	1
460	0	1
461	0	1
			==> MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=1812758612,DigestOffset=1656,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		90	0	0.00
CONT_ASSIGN	138	1	0	0.00
ALWAYS	153	68	0	0.00
CONT_ASSIGN	323	1	0	0.00
CONT_ASSIGN	325	1	0	0.00
CONT_ASSIGN	331	1	0	0.00
CONT_ASSIGN	338	1	0	0.00
CONT_ASSIGN	339	1	0	0.00
CONT_ASSIGN	343	1	0	0.00
CONT_ASSIGN	347	1	0	0.00
CONT_ASSIGN	384	1	0	0.00
CONT_ASSIGN	409	1	0	0.00
CONT_ASSIGN	443	1	0	0.00
ALWAYS	450	3	0	0.00
ALWAYS	453	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	0	1
153	0	1
156	0	1
159	0	1
160	0	1
163	0	1
164	0	1
165	0	1
168	0	1
171	0	1
172	0	1
173	0	1
175	0	1
180	0	1
182	0	1
183	0	1
185		unreachable
			==> MISSING_ELSE
194	0	1
195	0	1
196	0	1
			==> MISSING_ELSE
204	0	1
205	0	1
206	0	1
207	0	1
209	0	1
210	0	1
			==> MISSING_ELSE
213	0	1
214	0	1
			==> MISSING_ELSE
222	0	1
223	0	1
224	0	1
225	0	1
226	0	1
			==> MISSING_ELSE
235	0	1
237	0	1
238	0	1
239	0	1
240	0	1
241	0	1
			==> MISSING_ELSE
244	0	1
245	0	1
246	0	1
247	0	1
255	0	1
256	0	1
257	0	1
258	0	1
259	0	1
261	0	1
262	0	1
			==> MISSING_ELSE
265	0	1
266	0	1
268	0	1
			==> MISSING_ELSE
277	0	1
278	0	1
			==> MISSING_ELSE
282	0	1
283	0	1
284	0	1
285	0	1
286	0	1
287	0	1
			==> MISSING_ELSE
303	0	1
304	0	1
305	0	1
306	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
310	0	1
311	0	1
312	0	1
313	0	1
314	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
323	0	1
325	0	1
331	0	1
338	0	1
339	0	1
343	0	1
347	0	1
384	0	1
409	0	1
443	0	1
450	0	3
453	0	1
454	0	1
455	0	1
456	0	1
458	0	1
459	0	1
460	0	1
461	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	31	0	0.00
Logical	31	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       261
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       277
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       305
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       313
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       325
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       325
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       325
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       338
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       338
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       347
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       347
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       384
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       409
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       409
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=1812758612,DigestOffset=1656,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	0	0.00
Logical	34	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       261
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       277
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       305
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       313
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       325
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       325
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       325
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       331
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b01101100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       338
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       338
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       347
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       347
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       384
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       409
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       409
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=135037012,DigestOffset=856,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	0	0.00
Logical	34	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       261
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       277
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       305
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       313
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       325
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       325
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       325
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       331
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       338
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       338
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       347
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       347
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       384
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       409
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       409
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Module : otp_ctrl_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	0	0.00	(Not included in score)
Transitions	14	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	213	Not Covered
IdleSt	185	Not Covered
InitSt	183	Not Covered
InitWaitSt	196	Not Covered
ReadSt	225	Not Covered
ReadWaitSt	241	Not Covered
ResetSt	179	Not Covered

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	304	Not Covered
IdleSt->ReadSt	225	Not Covered
InitSt->ErrorSt	304	Not Covered
InitSt->InitWaitSt	196	Not Covered
InitWaitSt->ErrorSt	213	Not Covered
InitWaitSt->IdleSt	207	Not Covered
ReadSt->ErrorSt	304	Not Covered
ReadSt->IdleSt	244	Not Covered
ReadSt->ReadWaitSt	241	Not Covered
ReadWaitSt->ErrorSt	265	Not Covered
ReadWaitSt->IdleSt	259	Not Covered
ResetSt->ErrorSt	304	Not Covered
ResetSt->IdleSt	185	Not Covered
ResetSt->InitSt	183	Not Covered

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	20	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	245	Not Covered
CheckFailError	306	Not Covered
FsmStateError	278	Not Covered
MacroEccCorrError	210	Not Covered
NoError	224	Not Covered

transitions	Line No.	Covered	Tests
AccessError->CheckFailError	306	Not Covered
AccessError->FsmStateError	314	Not Covered
AccessError->MacroEccCorrError	210	Not Covered
AccessError->NoError	224	Not Covered
CheckFailError->AccessError	245	Not Covered
CheckFailError->FsmStateError	314	Not Covered
CheckFailError->MacroEccCorrError	210	Not Covered
CheckFailError->NoError	224	Not Covered
FsmStateError->AccessError	245	Not Covered
FsmStateError->CheckFailError	306	Not Covered
FsmStateError->MacroEccCorrError	210	Not Covered
FsmStateError->NoError	224	Not Covered
MacroEccCorrError->AccessError	245	Not Covered
MacroEccCorrError->CheckFailError	306	Not Covered
MacroEccCorrError->FsmStateError	314	Not Covered
MacroEccCorrError->NoError	224	Not Covered
NoError->AccessError	245	Not Covered
NoError->CheckFailError	306	Not Covered
NoError->FsmStateError	278	Not Covered
NoError->MacroEccCorrError	210	Not Covered

---

Branch Coverage for Module : otp_ctrl_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	0	0.00
TERNARY	325	2	0	0.00
TERNARY	338	2	0	0.00
TERNARY	347	2	0	0.00
TERNARY	384	2	0	0.00
TERNARY	409	2	0	0.00
CASE	175	23	0	0.00
IF	303	3	0	0.00
IF	310	3	0	0.00
IF	450	2	0	0.00
IF	453	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	325	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	338	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	347	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	384	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	409	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	175	case (state_q)
-2-:	180	if (init_req_i)
-3-:	182	if (1'b1)
-4-:	195	if (otp_gnt_i)
-5-:	204	if (otp_rvalid_i)
-6-:	206	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-7-:	209	if ((otp_err_e'(otp_err_i) != NoError))
-8-:	223	if (tlul_req_i)
-9-:	237	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	240	if (otp_gnt_i)
-11-:	256	if (otp_rvalid_i)
-12-:	258	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-13-:	261	if ((otp_err_e'(otp_err_i) != NoError))
-14-:	277	if ((error_q == NoError))
-15-:	282	if (pending_tlul_error_q)
-16-:	285	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	303	if (ecc_err)
-2-:	305	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	310	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	313	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	450	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	453	if ((!rst_ni))
-2-:	460	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		89	0	0.00
CONT_ASSIGN	138	1	0	0.00
ALWAYS	153	67	0	0.00
CONT_ASSIGN	323	1	0	0.00
CONT_ASSIGN	325	1	0	0.00
CONT_ASSIGN	328	1	0	0.00
CONT_ASSIGN	338	1	0	0.00
CONT_ASSIGN	339	1	0	0.00
CONT_ASSIGN	343	1	0	0.00
CONT_ASSIGN	347	1	0	0.00
CONT_ASSIGN	384	1	0	0.00
CONT_ASSIGN	409	1	0	0.00
CONT_ASSIGN	443	1	0	0.00
ALWAYS	450	3	0	0.00
ALWAYS	453	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	0	1
153	0	1
156	0	1
159	0	1
160	0	1
163	0	1
164	0	1
165	0	1
168	0	1
171	0	1
172	0	1
173	0	1
175	0	1
180	0	1
182	0	1
183	0	1
185		unreachable
			==> MISSING_ELSE
194	0	1
195	0	1
196	0	1
			==> MISSING_ELSE
204	0	1
205	0	1
206	0	1
207	0	1
209	0	1
210	0	1
			==> MISSING_ELSE
213	0	1
214	0	1
			==> MISSING_ELSE
222	0	1
223	0	1
224	0	1
225	0	1
226	0	1
			==> MISSING_ELSE
235	0	1
237	0	1
238	0	1
239	0	1
240	0	1
241	0	1
			==> MISSING_ELSE
244	0	1
245	0	1
246	0	1
247	0	1
255	0	1
256	0	1
257	0	1
258	0	1
259	0	1
261	0	1
262	0	1
			==> MISSING_ELSE
265	0	1
266	0	1
268	0	1
			==> MISSING_ELSE
277	0	1
278		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
282	0	1
283	0	1
284	0	1
285	0	1
286	0	1
287	0	1
			==> MISSING_ELSE
303	0	1
304	0	1
305	0	1
306	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
310	0	1
311	0	1
312	0	1
313	0	1
314	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
323	0	1
325	0	1
328	0	1
338	0	1
339	0	1
343	0	1
347	0	1
384	0	1
409	0	1
443	0	1
450	0	3
453	0	1
454	0	1
455	0	1
456	0	1
458	0	1
459	0	1
460	0	1
461	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	31	0	0.00
Logical	31	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       261
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       277
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       305
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       313
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       325
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       325
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       325
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       338
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       338
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       347
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       347
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       384
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       409
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       409
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	0	0.00	(Not included in score)
Transitions	14	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	213	Not Covered
IdleSt	185	Not Covered
InitSt	183	Not Covered
InitWaitSt	196	Not Covered
ReadSt	225	Not Covered
ReadWaitSt	241	Not Covered
ResetSt	179	Not Covered

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	304	Not Covered
IdleSt->ReadSt	225	Not Covered
InitSt->ErrorSt	304	Not Covered
InitSt->InitWaitSt	196	Not Covered
InitWaitSt->ErrorSt	213	Not Covered
InitWaitSt->IdleSt	207	Not Covered
ReadSt->ErrorSt	304	Not Covered
ReadSt->IdleSt	244	Not Covered
ReadSt->ReadWaitSt	241	Not Covered
ReadWaitSt->ErrorSt	265	Not Covered
ReadWaitSt->IdleSt	259	Not Covered
ResetSt->ErrorSt	304	Not Covered
ResetSt->IdleSt	185	Not Covered
ResetSt->InitSt	183	Not Covered

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	11	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	245	Not Covered
CheckFailError	306	Not Covered
FsmStateError	278	Not Covered
MacroEccCorrError	210	Not Covered
NoError	224	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	306	Excluded		VC_COV_UNR
AccessError->FsmStateError	314	Not Covered
AccessError->MacroEccCorrError	210	Excluded		VC_COV_UNR
AccessError->NoError	224	Not Covered
CheckFailError->AccessError	245	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	314	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	210	Excluded		VC_COV_UNR
CheckFailError->NoError	224	Not Covered
FsmStateError->AccessError	245	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	306	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	210	Excluded		VC_COV_UNR
FsmStateError->NoError	224	Not Covered
MacroEccCorrError->AccessError	245	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	306	Not Covered
MacroEccCorrError->FsmStateError	314	Not Covered
MacroEccCorrError->NoError	224	Not Covered
NoError->AccessError	245	Not Covered
NoError->CheckFailError	306	Not Covered
NoError->FsmStateError	278	Not Covered
NoError->MacroEccCorrError	210	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	0	0.00
TERNARY	325	2	0	0.00
TERNARY	338	2	0	0.00
TERNARY	347	2	0	0.00
TERNARY	384	2	0	0.00
TERNARY	409	2	0	0.00
CASE	175	23	0	0.00
IF	303	3	0	0.00
IF	310	3	0	0.00
IF	450	2	0	0.00
IF	453	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	325	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	338	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	347	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	384	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	409	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	175	case (state_q)
-2-:	180	if (init_req_i)
-3-:	182	if (1'b1)
-4-:	195	if (otp_gnt_i)
-5-:	204	if (otp_rvalid_i)
-6-:	206	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-7-:	209	if ((otp_err_e'(otp_err_i) != NoError))
-8-:	223	if (tlul_req_i)
-9-:	237	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	240	if (otp_gnt_i)
-11-:	256	if (otp_rvalid_i)
-12-:	258	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-13-:	261	if ((otp_err_e'(otp_err_i) != NoError))
-14-:	277	if ((error_q == NoError))
-15-:	282	if (pending_tlul_error_q)
-16-:	285	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	303	if (ecc_err)
-2-:	305	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	310	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	313	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	450	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	453	if ((!rst_ni))
-2-:	460	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		89	0	0.00
CONT_ASSIGN	138	1	0	0.00
ALWAYS	153	67	0	0.00
CONT_ASSIGN	323	1	0	0.00
CONT_ASSIGN	325	1	0	0.00
CONT_ASSIGN	331	1	0	0.00
CONT_ASSIGN	338	1	0	0.00
CONT_ASSIGN	339	1	0	0.00
CONT_ASSIGN	343	1	0	0.00
CONT_ASSIGN	347	1	0	0.00
CONT_ASSIGN	384	1	0	0.00
CONT_ASSIGN	409	1	0	0.00
CONT_ASSIGN	443	1	0	0.00
ALWAYS	450	3	0	0.00
ALWAYS	453	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	0	1
153	0	1
156	0	1
159	0	1
160	0	1
163	0	1
164	0	1
165	0	1
168	0	1
171	0	1
172	0	1
173	0	1
175	0	1
180	0	1
182	0	1
183	0	1
185		unreachable
			==> MISSING_ELSE
194	0	1
195	0	1
196	0	1
			==> MISSING_ELSE
204	0	1
205	0	1
206	0	1
207	0	1
209	0	1
210	0	1
			==> MISSING_ELSE
213	0	1
214	0	1
			==> MISSING_ELSE
222	0	1
223	0	1
224	0	1
225	0	1
226	0	1
			==> MISSING_ELSE
235	0	1
237	0	1
238	0	1
239	0	1
240	0	1
241	0	1
			==> MISSING_ELSE
244	0	1
245	0	1
246	0	1
247	0	1
255	0	1
256	0	1
257	0	1
258	0	1
259	0	1
261	0	1
262	0	1
			==> MISSING_ELSE
265	0	1
266	0	1
268	0	1
			==> MISSING_ELSE
277	0	1
278		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
282	0	1
283	0	1
284	0	1
285	0	1
286	0	1
287	0	1
			==> MISSING_ELSE
303	0	1
304	0	1
305	0	1
306	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
310	0	1
311	0	1
312	0	1
313	0	1
314	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
323	0	1
325	0	1
331	0	1
338	0	1
339	0	1
343	0	1
347	0	1
384	0	1
409	0	1
443	0	1
450	0	3
453	0	1
454	0	1
455	0	1
456	0	1
458	0	1
459	0	1
460	0	1
461	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	0	0.00
Logical	34	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       261
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       277
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       305
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       313
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       325
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       325
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       325
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       331
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       338
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       338
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       347
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       347
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       384
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       409
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       409
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	0	0.00	(Not included in score)
Transitions	14	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	213	Not Covered
IdleSt	185	Not Covered
InitSt	183	Not Covered
InitWaitSt	196	Not Covered
ReadSt	225	Not Covered
ReadWaitSt	241	Not Covered
ResetSt	179	Not Covered

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	304	Not Covered
IdleSt->ReadSt	225	Not Covered
InitSt->ErrorSt	304	Not Covered
InitSt->InitWaitSt	196	Not Covered
InitWaitSt->ErrorSt	213	Not Covered
InitWaitSt->IdleSt	207	Not Covered
ReadSt->ErrorSt	304	Not Covered
ReadSt->IdleSt	244	Not Covered
ReadSt->ReadWaitSt	241	Not Covered
ReadWaitSt->ErrorSt	265	Not Covered
ReadWaitSt->IdleSt	259	Not Covered
ResetSt->ErrorSt	304	Not Covered
ResetSt->IdleSt	185	Not Covered
ResetSt->InitSt	183	Not Covered

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	11	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	245	Not Covered
CheckFailError	306	Not Covered
FsmStateError	278	Not Covered
MacroEccCorrError	210	Not Covered
NoError	224	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	306	Excluded		VC_COV_UNR
AccessError->FsmStateError	314	Not Covered
AccessError->MacroEccCorrError	210	Excluded		VC_COV_UNR
AccessError->NoError	224	Not Covered
CheckFailError->AccessError	245	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	314	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	210	Excluded		VC_COV_UNR
CheckFailError->NoError	224	Not Covered
FsmStateError->AccessError	245	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	306	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	210	Excluded		VC_COV_UNR
FsmStateError->NoError	224	Not Covered
MacroEccCorrError->AccessError	245	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	306	Not Covered
MacroEccCorrError->FsmStateError	314	Not Covered
MacroEccCorrError->NoError	224	Not Covered
NoError->AccessError	245	Not Covered
NoError->CheckFailError	306	Not Covered
NoError->FsmStateError	278	Not Covered
NoError->MacroEccCorrError	210	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	0	0.00
TERNARY	325	2	0	0.00
TERNARY	338	2	0	0.00
TERNARY	347	2	0	0.00
TERNARY	384	2	0	0.00
TERNARY	409	2	0	0.00
CASE	175	23	0	0.00
IF	303	3	0	0.00
IF	310	3	0	0.00
IF	450	2	0	0.00
IF	453	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	325	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	338	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	347	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	384	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	409	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	175	case (state_q)
-2-:	180	if (init_req_i)
-3-:	182	if (1'b1)
-4-:	195	if (otp_gnt_i)
-5-:	204	if (otp_rvalid_i)
-6-:	206	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-7-:	209	if ((otp_err_e'(otp_err_i) != NoError))
-8-:	223	if (tlul_req_i)
-9-:	237	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	240	if (otp_gnt_i)
-11-:	256	if (otp_rvalid_i)
-12-:	258	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-13-:	261	if ((otp_err_e'(otp_err_i) != NoError))
-14-:	277	if ((error_q == NoError))
-15-:	282	if (pending_tlul_error_q)
-16-:	285	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	303	if (ecc_err)
-2-:	305	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	310	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	313	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	450	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	453	if ((!rst_ni))
-2-:	460	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		89	0	0.00
CONT_ASSIGN	138	1	0	0.00
ALWAYS	153	67	0	0.00
CONT_ASSIGN	323	1	0	0.00
CONT_ASSIGN	325	1	0	0.00
CONT_ASSIGN	331	1	0	0.00
CONT_ASSIGN	338	1	0	0.00
CONT_ASSIGN	339	1	0	0.00
CONT_ASSIGN	343	1	0	0.00
CONT_ASSIGN	347	1	0	0.00
CONT_ASSIGN	384	1	0	0.00
CONT_ASSIGN	409	1	0	0.00
CONT_ASSIGN	443	1	0	0.00
ALWAYS	450	3	0	0.00
ALWAYS	453	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	0	1
153	0	1
156	0	1
159	0	1
160	0	1
163	0	1
164	0	1
165	0	1
168	0	1
171	0	1
172	0	1
173	0	1
175	0	1
180	0	1
182	0	1
183	0	1
185		unreachable
			==> MISSING_ELSE
194	0	1
195	0	1
196	0	1
			==> MISSING_ELSE
204	0	1
205	0	1
206	0	1
207	0	1
209	0	1
210	0	1
			==> MISSING_ELSE
213	0	1
214	0	1
			==> MISSING_ELSE
222	0	1
223	0	1
224	0	1
225	0	1
226	0	1
			==> MISSING_ELSE
235	0	1
237	0	1
238	0	1
239	0	1
240	0	1
241	0	1
			==> MISSING_ELSE
244	0	1
245	0	1
246	0	1
247	0	1
255	0	1
256	0	1
257	0	1
258	0	1
259	0	1
261	0	1
262	0	1
			==> MISSING_ELSE
265	0	1
266	0	1
268	0	1
			==> MISSING_ELSE
277	0	1
278		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
282	0	1
283	0	1
284	0	1
285	0	1
286	0	1
287	0	1
			==> MISSING_ELSE
303	0	1
304	0	1
305	0	1
306	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
310	0	1
311	0	1
312	0	1
313	0	1
314	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
323	0	1
325	0	1
331	0	1
338	0	1
339	0	1
343	0	1
347	0	1
384	0	1
409	0	1
443	0	1
450	0	3
453	0	1
454	0	1
455	0	1
456	0	1
458	0	1
459	0	1
460	0	1
461	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	0	0.00
Logical	34	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       261
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       277
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       305
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       313
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       325
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       325
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       325
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       331
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b01101100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       338
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       338
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       347
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       347
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       384
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       409
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       409
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	0	0.00	(Not included in score)
Transitions	14	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	213	Not Covered
IdleSt	185	Not Covered
InitSt	183	Not Covered
InitWaitSt	196	Not Covered
ReadSt	225	Not Covered
ReadWaitSt	241	Not Covered
ResetSt	179	Not Covered

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	304	Not Covered
IdleSt->ReadSt	225	Not Covered
InitSt->ErrorSt	304	Not Covered
InitSt->InitWaitSt	196	Not Covered
InitWaitSt->ErrorSt	213	Not Covered
InitWaitSt->IdleSt	207	Not Covered
ReadSt->ErrorSt	304	Not Covered
ReadSt->IdleSt	244	Not Covered
ReadSt->ReadWaitSt	241	Not Covered
ReadWaitSt->ErrorSt	265	Not Covered
ReadWaitSt->IdleSt	259	Not Covered
ResetSt->ErrorSt	304	Not Covered
ResetSt->IdleSt	185	Not Covered
ResetSt->InitSt	183	Not Covered

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	11	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	245	Not Covered
CheckFailError	306	Not Covered
FsmStateError	278	Not Covered
MacroEccCorrError	210	Not Covered
NoError	224	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	306	Excluded		VC_COV_UNR
AccessError->FsmStateError	314	Not Covered
AccessError->MacroEccCorrError	210	Excluded		VC_COV_UNR
AccessError->NoError	224	Not Covered
CheckFailError->AccessError	245	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	314	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	210	Excluded		VC_COV_UNR
CheckFailError->NoError	224	Not Covered
FsmStateError->AccessError	245	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	306	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	210	Excluded		VC_COV_UNR
FsmStateError->NoError	224	Not Covered
MacroEccCorrError->AccessError	245	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	306	Not Covered
MacroEccCorrError->FsmStateError	314	Not Covered
MacroEccCorrError->NoError	224	Not Covered
NoError->AccessError	245	Not Covered
NoError->CheckFailError	306	Not Covered
NoError->FsmStateError	278	Not Covered
NoError->MacroEccCorrError	210	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	0	0.00
TERNARY	325	2	0	0.00
TERNARY	338	2	0	0.00
TERNARY	347	2	0	0.00
TERNARY	384	2	0	0.00
TERNARY	409	2	0	0.00
CASE	175	23	0	0.00
IF	303	3	0	0.00
IF	310	3	0	0.00
IF	450	2	0	0.00
IF	453	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	325	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	338	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	347	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	384	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	409	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	175	case (state_q)
-2-:	180	if (init_req_i)
-3-:	182	if (1'b1)
-4-:	195	if (otp_gnt_i)
-5-:	204	if (otp_rvalid_i)
-6-:	206	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-7-:	209	if ((otp_err_e'(otp_err_i) != NoError))
-8-:	223	if (tlul_req_i)
-9-:	237	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	240	if (otp_gnt_i)
-11-:	256	if (otp_rvalid_i)
-12-:	258	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-13-:	261	if ((otp_err_e'(otp_err_i) != NoError))
-14-:	277	if ((error_q == NoError))
-15-:	282	if (pending_tlul_error_q)
-16-:	285	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	303	if (ecc_err)
-2-:	305	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	310	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	313	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	450	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	453	if ((!rst_ni))
-2-:	460	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered