Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.67						86.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	86.67						86.67

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.67						86.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.67						86.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
7.74	0.00	0.00	30.95		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	13	86.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	13	86.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2976408	8990	0	0
check_regwen_rd_A	2976408	1874	0	0
check_timeout_rd_A	2976408	1065	0	0
check_trigger_regwen_rd_A	2976408	2073	0	0
consistency_check_period_rd_A	2976408	2080	0	0
creator_sw_cfg_read_lock_rd_A	2976408	1065	0	0
direct_access_address_rd_A	2976408	37	0	0
direct_access_wdata_0_rd_A	2976408	0	0	0
direct_access_wdata_1_rd_A	2976408	0	0	0
integrity_check_period_rd_A	2976408	1974	0	0
intr_enable_rd_A	2976408	2109	0	0
owner_sw_cfg_read_lock_rd_A	2976408	944	0	0
rot_creator_auth_codesign_read_lock_rd_A	2976408	1214	0	0
rot_creator_auth_state_read_lock_rd_A	2976408	1099	0	0
vendor_test_read_lock_rd_A	2976408	1007	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2976408	8990	0	0
T1	14074	408	0	0
T2	3246	0	0	0
T3	3541	0	0	0
T4	61746	3	0	0
T5	0	5	0	0
T6	0	5	0	0
T7	6317	311	0	0
T8	7088	372	0	0
T9	3404	0	0	0
T10	3532	0	0	0
T14	3361	0	0	0
T17	0	7	0	0
T18	4930	0	0	0
T19	0	465	0	0
T20	0	10	0	0
T25	0	1	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2976408	1874	0	0
T6	121875	65	0	0
T12	3728	0	0	0
T15	3271	0	0	0
T16	4776	9	0	0
T17	120068	0	0	0
T19	8428	0	0	0
T25	67725	0	0	0
T28	8594	0	0	0
T35	3235	0	0	0
T38	0	26	0	0
T39	0	8	0	0
T40	0	11	0	0
T51	0	29	0	0
T57	0	10	0	0
T59	3274	0	0	0
T61	0	38	0	0
T62	0	1	0	0
T63	0	211	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2976408	1065	0	0
T22	7167	0	0	0
T23	10122	0	0	0
T24	7830	0	0	0
T37	3158	0	0	0
T38	0	10	0	0
T39	0	21	0	0
T45	0	404	0	0
T47	126627	0	0	0
T48	3672	0	0	0
T51	0	9	0	0
T57	11059	29	0	0
T61	0	26	0	0
T63	0	231	0	0
T64	0	21	0	0
T65	0	51	0	0
T66	0	13	0	0
T67	3824	0	0	0
T68	3356	0	0	0
T69	4830	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2976408	2073	0	0
T6	121875	73	0	0
T12	3728	0	0	0
T15	3271	0	0	0
T16	4776	14	0	0
T17	120068	0	0	0
T19	8428	0	0	0
T21	0	8	0	0
T25	67725	0	0	0
T28	8594	0	0	0
T35	3235	0	0	0
T39	0	27	0	0
T40	0	9	0	0
T51	0	15	0	0
T57	0	29	0	0
T59	3274	0	0	0
T61	0	23	0	0
T63	0	255	0	0
T70	0	195	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2976408	2080	0	0
T5	7229	12	0	0
T6	121875	89	0	0
T12	3728	0	0	0
T16	4776	10	0	0
T17	120068	0	0	0
T19	8428	0	0	0
T21	0	3	0	0
T25	67725	0	0	0
T28	8594	0	0	0
T35	3235	0	0	0
T38	0	59	0	0
T39	0	19	0	0
T40	0	10	0	0
T51	0	8	0	0
T57	0	46	0	0
T59	3274	0	0	0
T62	0	4	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2976408	1065	0	0
T22	7167	0	0	0
T23	10122	0	0	0
T24	7830	0	0	0
T37	3158	0	0	0
T38	0	45	0	0
T39	0	19	0	0
T45	0	421	0	0
T47	126627	0	0	0
T48	3672	0	0	0
T51	0	3	0	0
T57	11059	15	0	0
T61	0	8	0	0
T63	0	216	0	0
T64	0	43	0	0
T65	0	80	0	0
T66	0	3	0	0
T67	3824	0	0	0
T68	3356	0	0	0
T69	4830	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2976408	37	0	0
T13	3513	0	0	0
T21	6897	5	0	0
T26	119879	0	0	0
T27	61496	0	0	0
T30	4115	0	0	0
T31	11587	0	0	0
T32	5962	0	0	0
T51	0	14	0	0
T66	0	6	0	0
T71	0	6	0	0
T72	0	6	0	0
T73	3270	0	0	0
T74	3281	0	0	0
T75	3578	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2976408	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2976408	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2976408	1974	0	0
T5	7229	7	0	0
T6	121875	83	0	0
T12	3728	0	0	0
T16	4776	8	0	0
T17	120068	0	0	0
T19	8428	0	0	0
T25	67725	0	0	0
T28	8594	0	0	0
T35	3235	0	0	0
T38	0	48	0	0
T39	0	31	0	0
T40	0	12	0	0
T51	0	19	0	0
T57	0	35	0	0
T59	3274	0	0	0
T61	0	7	0	0
T63	0	234	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2976408	2109	0	0
T5	7229	9	0	0
T6	121875	111	0	0
T11	3965	4	0	0
T12	3728	0	0	0
T13	0	13	0	0
T16	4776	7	0	0
T17	120068	0	0	0
T19	8428	0	0	0
T21	0	17	0	0
T25	67725	0	0	0
T28	8594	0	0	0
T35	3235	10	0	0
T51	0	18	0	0
T57	0	46	0	0
T68	0	10	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2976408	944	0	0
T5	7229	5	0	0
T6	121875	0	0	0
T12	3728	0	0	0
T16	4776	0	0	0
T17	120068	0	0	0
T19	8428	0	0	0
T25	67725	0	0	0
T28	8594	0	0	0
T35	3235	0	0	0
T38	0	16	0	0
T39	0	18	0	0
T45	0	330	0	0
T51	0	14	0	0
T57	0	49	0	0
T59	3274	0	0	0
T61	0	17	0	0
T63	0	185	0	0
T64	0	66	0	0
T65	0	18	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2976408	1214	0	0
T5	7229	2	0	0
T6	121875	0	0	0
T12	3728	0	0	0
T16	4776	0	0	0
T17	120068	0	0	0
T19	8428	0	0	0
T21	0	3	0	0
T25	67725	0	0	0
T28	8594	0	0	0
T35	3235	0	0	0
T38	0	14	0	0
T39	0	36	0	0
T51	0	9	0	0
T57	0	96	0	0
T59	3274	0	0	0
T61	0	31	0	0
T63	0	238	0	0
T64	0	76	0	0
T65	0	54	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2976408	1099	0	0
T13	3513	0	0	0
T21	6897	7	0	0
T26	119879	0	0	0
T27	61496	0	0	0
T30	4115	0	0	0
T31	11587	0	0	0
T32	5962	0	0	0
T38	0	2	0	0
T39	0	34	0	0
T45	0	413	0	0
T51	0	5	0	0
T57	0	38	0	0
T61	0	1	0	0
T63	0	230	0	0
T64	0	27	0	0
T65	0	67	0	0
T73	3270	0	0	0
T74	3281	0	0	0
T75	3578	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2976408	1007	0	0
T22	7167	0	0	0
T23	10122	0	0	0
T24	7830	0	0	0
T37	3158	0	0	0
T38	0	18	0	0
T39	0	33	0	0
T45	0	373	0	0
T47	126627	0	0	0
T48	3672	0	0	0
T51	0	10	0	0
T57	11059	44	0	0
T61	0	42	0	0
T63	0	242	0	0
T64	0	12	0	0
T65	0	19	0	0
T66	0	9	0	0
T67	3824	0	0	0
T68	3356	0	0	0
T69	4830	0	0	0