| | | | | | | |
| core_tlul_assert_device |
33.33 |
0.00 |
|
|
|
0.00 |
100.00 |
| gen_alert_tx[0].u_prim_alert_sender |
70.00 |
|
|
70.00 |
|
|
|
| gen_alert_tx[1].u_prim_alert_sender |
70.00 |
|
|
70.00 |
|
|
|
| gen_alert_tx[2].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| gen_alert_tx[3].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
gen_alert_tx[4].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| gen_bufs[0].u_prim_mubi8_sender_read_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[0].u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[10].u_prim_mubi8_sender_read_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[10].u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[1].u_prim_mubi8_sender_read_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[1].u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[2].u_prim_mubi8_sender_read_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[2].u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[3].u_prim_mubi8_sender_read_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[3].u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[4].u_prim_mubi8_sender_read_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[4].u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[5].u_prim_mubi8_sender_read_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[5].u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[6].u_prim_mubi8_sender_read_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[6].u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[7].u_prim_mubi8_sender_read_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[7].u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[8].u_prim_mubi8_sender_read_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[8].u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[9].u_prim_mubi8_sender_read_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_bufs[9].u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_partitions[0].gen_unbuffered.u_part_unbuf |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| gen_digest_write_lock.u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_ecc_reg.u_otp_ctrl_ecc_reg |
0.00 |
0.00 |
|
0.00 |
|
0.00 |
|
| gen_ecc_dec[0].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_secded_inv_72_64_enc |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_mubi8_sender_read_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_prim_mubi8_sender_write_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_partitions[10].gen_lifecycle.u_part_buf |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| u_otp_ctrl_ecc_reg |
0.00 |
0.00 |
|
0.00 |
|
0.00 |
|
| gen_ecc_dec[0].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[10].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[1].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[2].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[3].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[4].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[5].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[6].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[7].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[8].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[9].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_secded_inv_72_64_enc |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_count |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_mubi8_sender_read_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_prim_mubi8_sender_write_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_partitions[1].gen_unbuffered.u_part_unbuf |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| gen_digest_write_lock.u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_ecc_reg.u_otp_ctrl_ecc_reg |
0.00 |
0.00 |
|
0.00 |
|
0.00 |
|
| gen_ecc_dec[0].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_secded_inv_72_64_enc |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_mubi8_sender_read_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_prim_mubi8_sender_write_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_partitions[2].gen_unbuffered.u_part_unbuf |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| gen_digest_write_lock.u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_ecc_reg.u_otp_ctrl_ecc_reg |
0.00 |
0.00 |
|
0.00 |
|
0.00 |
|
| gen_ecc_dec[0].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_secded_inv_72_64_enc |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_mubi8_sender_read_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_prim_mubi8_sender_write_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_partitions[3].gen_unbuffered.u_part_unbuf |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| gen_digest_write_lock.u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_ecc_reg.u_otp_ctrl_ecc_reg |
0.00 |
0.00 |
|
0.00 |
|
0.00 |
|
| gen_ecc_dec[0].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_secded_inv_72_64_enc |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_mubi8_sender_read_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_prim_mubi8_sender_write_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_partitions[4].gen_unbuffered.u_part_unbuf |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| gen_digest_write_lock.u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_ecc_reg.u_otp_ctrl_ecc_reg |
0.00 |
0.00 |
|
0.00 |
|
0.00 |
|
| gen_ecc_dec[0].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_secded_inv_72_64_enc |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_mubi8_sender_read_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_prim_mubi8_sender_write_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_partitions[5].gen_buffered.u_part_buf |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| gen_digest_write_lock.u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_otp_ctrl_ecc_reg |
0.00 |
0.00 |
|
0.00 |
|
0.00 |
|
| gen_ecc_dec[0].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[1].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[2].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[3].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[4].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[5].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[6].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[7].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[8].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_secded_inv_72_64_enc |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_count |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_mubi8_sender_read_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_prim_mubi8_sender_write_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_partitions[6].gen_buffered.u_part_buf |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| gen_digest_write_lock.u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_otp_ctrl_ecc_reg |
0.00 |
0.00 |
|
0.00 |
|
0.00 |
|
| gen_ecc_dec[0].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[1].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_secded_inv_72_64_enc |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_count |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_mubi8_sender_read_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_prim_mubi8_sender_write_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_partitions[7].gen_buffered.u_part_buf |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| gen_digest_read_lock.u_prim_mubi8_sender_read_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_digest_write_lock.u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_otp_ctrl_ecc_reg |
0.00 |
0.00 |
|
0.00 |
|
0.00 |
|
| gen_ecc_dec[0].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[1].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[2].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[3].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[4].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_secded_inv_72_64_enc |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_count |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_mubi8_sender_read_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_prim_mubi8_sender_write_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_partitions[8].gen_buffered.u_part_buf |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| gen_digest_read_lock.u_prim_mubi8_sender_read_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_digest_write_lock.u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_otp_ctrl_ecc_reg |
0.00 |
0.00 |
|
0.00 |
|
0.00 |
|
| gen_ecc_dec[0].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[10].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[1].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[2].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[3].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[4].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[5].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[6].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[7].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[8].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[9].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_secded_inv_72_64_enc |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_count |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_mubi8_sender_read_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_prim_mubi8_sender_write_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_partitions[9].gen_buffered.u_part_buf |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| gen_digest_read_lock.u_prim_mubi8_sender_read_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_digest_write_lock.u_prim_mubi8_sender_write_lock |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_otp_ctrl_ecc_reg |
0.00 |
0.00 |
|
0.00 |
|
0.00 |
|
| gen_ecc_dec[0].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[10].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[1].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[2].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[3].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[4].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[5].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[6].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[7].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[8].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| gen_ecc_dec[9].u_prim_secded_inv_72_64_dec |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_secded_inv_72_64_enc |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_count |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_mubi8_sender_read_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_prim_mubi8_sender_write_lock_pre |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_prim_buf.u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| otp_ctrl_core_csr_assert |
86.67 |
|
|
|
|
|
86.67 |
| prim_tlul_assert_device |
33.33 |
0.00 |
|
|
|
0.00 |
100.00 |
| u_edn_arb |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intr_error |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intr_operation_done |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_keygmr_key_valid |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_otp |
69.37 |
65.13 |
74.36 |
94.69 |
0.00 |
82.06 |
100.00 |
| gen_generic.u_impl_generic |
69.37 |
65.13 |
74.36 |
94.69 |
0.00 |
82.06 |
100.00 |
| u_dec |
0.00 |
0.00 |
0.00 |
|
|
|
|
| u_enc |
0.00 |
0.00 |
|
|
|
|
|
| u_prim_ram_1p_adv |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_mem |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_req_d_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_write_d_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_reg_top |
97.15 |
91.84 |
99.22 |
94.69 |
|
100.00 |
100.00 |
| u_chk |
100.00 |
100.00 |
|
100.00 |
|
|
100.00 |
| u_chk |
100.00 |
|
|
100.00 |
|
|
|
| u_tlul_data_integ_dec |
100.00 |
100.00 |
|
100.00 |
|
|
|
| u_data_chk |
100.00 |
|
|
100.00 |
|
|
|
| u_csr0_field0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr0_field1 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr0_field2 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr0_field3 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr0_field4 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr1_field0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr1_field1 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr1_field2 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr1_field3 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr1_field4 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr2 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr3_field0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
| u_csr3_field1 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
| u_csr3_field2 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
| u_csr3_field3 |
87.50 |
62.50 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
0.00 |
0.00 |
|
|
|
|
|
| u_csr3_field4 |
87.50 |
62.50 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
0.00 |
0.00 |
|
|
|
|
|
| u_csr3_field5 |
87.50 |
62.50 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
0.00 |
0.00 |
|
|
|
|
|
| u_csr3_field6 |
87.50 |
62.50 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
0.00 |
0.00 |
|
|
|
|
|
| u_csr3_field7 |
87.50 |
62.50 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
0.00 |
0.00 |
|
|
|
|
|
| u_csr3_field8 |
87.50 |
62.50 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
0.00 |
0.00 |
|
|
|
|
|
| u_csr4_field0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr4_field1 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr4_field2 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr4_field3 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr5_field0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr5_field1 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr5_field2 |
87.50 |
62.50 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
0.00 |
0.00 |
|
|
|
|
|
| u_csr5_field3 |
87.50 |
62.50 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
0.00 |
0.00 |
|
|
|
|
|
| u_csr5_field4 |
87.50 |
62.50 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
0.00 |
0.00 |
|
|
|
|
|
| u_csr5_field5 |
87.50 |
62.50 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
0.00 |
0.00 |
|
|
|
|
|
| u_csr5_field6 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr6_field0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr6_field1 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr6_field2 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr6_field3 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_csr7_field0 |
87.50 |
62.50 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
0.00 |
0.00 |
|
|
|
|
|
| u_csr7_field1 |
87.50 |
62.50 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
0.00 |
0.00 |
|
|
|
|
|
| u_csr7_field2 |
87.50 |
62.50 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
0.00 |
0.00 |
|
|
|
|
|
| u_csr7_field3 |
87.50 |
62.50 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
0.00 |
0.00 |
|
|
|
|
|
| u_prim_reg_we_check |
50.00 |
100.00 |
|
0.00 |
|
|
|
| u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| u_prim_onehot_check |
0.00 |
|
|
0.00 |
|
|
|
| u_reg_if |
98.97 |
97.14 |
98.75 |
|
|
100.00 |
100.00 |
| u_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| u_rsp_intg_gen |
83.33 |
66.67 |
|
|
|
|
100.00 |
| u_rsp_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
| gen_data_intg.u_tlul_data_integ_enc |
100.00 |
100.00 |
|
|
|
|
|
| u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
| gen_rsp_intg.u_rsp_gen |
100.00 |
100.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_otp_arb |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_otp_ctrl_dai |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| u_part_sel_idx |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_prim_count |
0.00 |
|
|
0.00 |
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_otp_ctrl_kdi |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| u_flash_addr_key_anchor |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_flash_data_key_anchor |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_key_out_anchor |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_secure_anchor_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_prim_count_entropy |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_count_seed |
0.00 |
|
|
0.00 |
|
|
|
| u_req_arb |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_sram_data_key_anchor |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_otp_ctrl_lci |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| u_prim_count |
0.00 |
|
|
0.00 |
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_otp_ctrl_lfsr_timer |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| u_prim_count_cnsty |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_count_integ |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_double_lfsr |
0.00 |
0.00 |
0.00 |
0.00 |
|
|
|
| gen_double_lfsr[0].u_prim_buf_input |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_double_lfsr[0].u_prim_buf_output |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_double_lfsr[0].u_prim_lfsr |
0.00 |
|
|
0.00 |
|
|
|
| gen_double_lfsr[1].u_prim_buf_input |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_double_lfsr[1].u_prim_buf_output |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_double_lfsr[1].u_prim_lfsr |
0.00 |
|
|
0.00 |
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_otp_ctrl_scrmbl |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| gen_anchor_digests[0].u_const_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_anchor_digests[0].u_iv_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_anchor_digests[1].u_const_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_anchor_digests[1].u_iv_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_anchor_digests[2].u_const_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_anchor_digests[2].u_iv_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_anchor_digests[3].u_const_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_anchor_digests[3].u_iv_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_anchor_keys[0].u_key_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_anchor_keys[1].u_key_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_anchor_keys[2].u_key_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_prim_count |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_present_dec |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_prim_present_enc |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_otp_init_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_otp_rsp_fifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_part_sel_idx |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_prim_edn_req |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_prim_packer_fifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_prim_sync_reqack_data |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_prim_sync_reqack |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_nrz_hs_protocol.ack_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_nrz_hs_protocol.req_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_prim_lc_sender_otp_broadcast_valid |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_flops.u_prim_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_secure_anchor_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_prim_lc_sender_rma_token_valid |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_no_flops.gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_no_flops.gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_no_flops.gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_no_flops.gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_prim_lc_sender_secrets_valid |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_no_flops.gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_no_flops.gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_no_flops.gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_no_flops.gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_prim_lc_sender_test_tokens_valid |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_no_flops.gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_no_flops.gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_no_flops.gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_no_flops.gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_prim_lc_sync_check_byp_en |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_flops.u_prim_flop_2sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_prim_lc_sync_creator_seed_sw_rw_en |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_flops.u_prim_flop_2sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_prim_lc_sync_dft_en |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_flops.u_prim_flop_2sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_prim_lc_sync_escalate_en |
0.00 |
0.00 |
|
|
|
0.00 |
|
| subtree... |
|
|
|
|
|
|
|
| u_prim_lc_sync_owner_seed_sw_rw_en |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_flops.u_prim_flop_2sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_prim_lc_sync_seed_hw_rd_en |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_flops.u_prim_flop_2sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_reg_core |
94.53 |
94.08 |
90.88 |
89.09 |
|
98.59 |
100.00 |
| u_alert_test_fatal_bus_integ_error |
100.00 |
100.00 |
|
|
|
|
|
| u_alert_test_fatal_check_error |
100.00 |
100.00 |
|
|
|
|
|
| u_alert_test_fatal_macro_error |
100.00 |
100.00 |
|
|
|
|
|
| u_alert_test_fatal_prim_otp_alert |
100.00 |
100.00 |
|
|
|
|
|
| u_alert_test_recov_prim_otp_alert |
100.00 |
100.00 |
|
|
|
|
|
| u_check_regwen |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
| u_check_timeout |
65.34 |
88.89 |
50.00 |
|
|
57.14 |
|
| wr_en_data_arb |
66.67 |
100.00 |
50.00 |
|
|
50.00 |
|
| u_check_trigger_consistency |
100.00 |
100.00 |
|
|
|
|
|
| u_check_trigger_integrity |
100.00 |
100.00 |
|
|
|
|
|
| u_check_trigger_regwen |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
| u_chk |
100.00 |
100.00 |
|
100.00 |
|
|
100.00 |
| u_chk |
100.00 |
|
|
100.00 |
|
|
|
| u_tlul_data_integ_dec |
100.00 |
100.00 |
|
100.00 |
|
|
|
| u_data_chk |
100.00 |
|
|
100.00 |
|
|
|
| u_consistency_check_period |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_creator_sw_cfg_digest_0 |
66.67 |
66.67 |
|
|
|
|
|
| u_creator_sw_cfg_digest_1 |
66.67 |
66.67 |
|
|
|
|
|
| u_creator_sw_cfg_read_lock |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
| u_direct_access_address |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_direct_access_cmd_digest |
100.00 |
100.00 |
|
|
|
|
|
| u_direct_access_cmd_rd |
100.00 |
100.00 |
|
|
|
|
|
| u_direct_access_cmd_wr |
100.00 |
100.00 |
|
|
|
|
|
| u_direct_access_rdata_0 |
100.00 |
100.00 |
|
|
|
|
|
| u_direct_access_rdata_1 |
100.00 |
100.00 |
|
|
|
|
|
| u_direct_access_regwen |
100.00 |
100.00 |
|
|
|
|
|
| u_direct_access_wdata_0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_direct_access_wdata_1 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_err_code_0 |
66.67 |
66.67 |
|
|
|
|
|
| u_err_code_1 |
100.00 |
100.00 |
|
|
|
|
|
| u_err_code_10 |
66.67 |
66.67 |
|
|
|
|
|
| u_err_code_11 |
100.00 |
100.00 |
|
|
|
|
|
| u_err_code_12 |
100.00 |
100.00 |
|
|
|
|
|
| u_err_code_2 |
100.00 |
100.00 |
|
|
|
|
|
| u_err_code_3 |
66.67 |
66.67 |
|
|
|
|
|
| u_err_code_4 |
66.67 |
66.67 |
|
|
|
|
|
| u_err_code_5 |
66.67 |
66.67 |
|
|
|
|
|
| u_err_code_6 |
66.67 |
66.67 |
|
|
|
|
|
| u_err_code_7 |
66.67 |
66.67 |
|
|
|
|
|
| u_err_code_8 |
66.67 |
66.67 |
|
|
|
|
|
| u_err_code_9 |
100.00 |
100.00 |
|
|
|
|
|
| u_hw_cfg0_digest_0 |
66.67 |
66.67 |
|
|
|
|
|
| u_hw_cfg0_digest_1 |
66.67 |
66.67 |
|
|
|
|
|
| u_hw_cfg1_digest_0 |
66.67 |
66.67 |
|
|
|
|
|
| u_hw_cfg1_digest_1 |
66.67 |
66.67 |
|
|
|
|
|
| u_integrity_check_period |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_intr_enable_otp_error |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_intr_enable_otp_operation_done |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_intr_state_otp_error |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
| u_intr_state_otp_operation_done |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
| u_intr_test_otp_error |
100.00 |
100.00 |
|
|
|
|
|
| u_intr_test_otp_operation_done |
100.00 |
100.00 |
|
|
|
|
|
| u_owner_sw_cfg_digest_0 |
66.67 |
66.67 |
|
|
|
|
|
| u_owner_sw_cfg_digest_1 |
66.67 |
66.67 |
|
|
|
|
|
| u_owner_sw_cfg_read_lock |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
| u_prim_reg_we_check |
50.00 |
100.00 |
|
0.00 |
|
|
|
| u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| u_prim_onehot_check |
0.00 |
|
|
0.00 |
|
|
|
| u_reg_if |
98.97 |
97.14 |
98.75 |
|
|
100.00 |
100.00 |
| u_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| u_rsp_intg_gen |
83.33 |
66.67 |
|
|
|
|
100.00 |
| u_rot_creator_auth_codesign_digest_0 |
66.67 |
66.67 |
|
|
|
|
|
| u_rot_creator_auth_codesign_digest_1 |
66.67 |
66.67 |
|
|
|
|
|
| u_rot_creator_auth_codesign_read_lock |
93.33 |
100.00 |
80.00 |
|
|
100.00 |
|
| wr_en_data_arb |
87.50 |
100.00 |
75.00 |
|
|
|
|
| u_rot_creator_auth_state_digest_0 |
66.67 |
66.67 |
|
|
|
|
|
| u_rot_creator_auth_state_digest_1 |
66.67 |
66.67 |
|
|
|
|
|
| u_rot_creator_auth_state_read_lock |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
| u_rsp_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
| gen_data_intg.u_tlul_data_integ_enc |
100.00 |
100.00 |
|
|
|
|
|
| u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
| gen_rsp_intg.u_rsp_gen |
100.00 |
100.00 |
|
|
|
|
|
| u_secret0_digest_0 |
66.67 |
66.67 |
|
|
|
|
|
| u_secret0_digest_1 |
66.67 |
66.67 |
|
|
|
|
|
| u_secret1_digest_0 |
66.67 |
66.67 |
|
|
|
|
|
| u_secret1_digest_1 |
66.67 |
66.67 |
|
|
|
|
|
| u_secret2_digest_0 |
66.67 |
66.67 |
|
|
|
|
|
| u_secret2_digest_1 |
66.67 |
66.67 |
|
|
|
|
|
| u_socket |
99.69 |
98.75 |
100.00 |
|
|
100.00 |
100.00 |
| fifo_h |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| reqfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
| rspfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
| gen_dfifo[0].fifo_d |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| reqfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
| rspfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
| gen_dfifo[1].fifo_d |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| reqfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
| rspfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
| u_status_bus_integ_error |
66.67 |
66.67 |
|
|
|
|
|
| u_status_check_pending |
66.67 |
66.67 |
|
|
|
|
|
| u_status_creator_sw_cfg_error |
66.67 |
66.67 |
|
|
|
|
|
| u_status_dai_error |
66.67 |
66.67 |
|
|
|
|
|
| u_status_dai_idle |
66.67 |
66.67 |
|
|
|
|
|
| u_status_hw_cfg0_error |
66.67 |
66.67 |
|
|
|
|
|
| u_status_hw_cfg1_error |
66.67 |
66.67 |
|
|
|
|
|
| u_status_key_deriv_fsm_error |
66.67 |
66.67 |
|
|
|
|
|
| u_status_lci_error |
66.67 |
66.67 |
|
|
|
|
|
| u_status_lfsr_fsm_error |
66.67 |
66.67 |
|
|
|
|
|
| u_status_life_cycle_error |
66.67 |
66.67 |
|
|
|
|
|
| u_status_owner_sw_cfg_error |
66.67 |
66.67 |
|
|
|
|
|
| u_status_rot_creator_auth_codesign_error |
66.67 |
66.67 |
|
|
|
|
|
| u_status_rot_creator_auth_state_error |
66.67 |
66.67 |
|
|
|
|
|
| u_status_scrambling_fsm_error |
66.67 |
66.67 |
|
|
|
|
|
| u_status_secret0_error |
66.67 |
66.67 |
|
|
|
|
|
| u_status_secret1_error |
66.67 |
66.67 |
|
|
|
|
|
| u_status_secret2_error |
66.67 |
66.67 |
|
|
|
|
|
| u_status_timeout_error |
66.67 |
66.67 |
|
|
|
|
|
| u_status_vendor_test_error |
66.67 |
66.67 |
|
|
|
|
|
| u_vendor_test_digest_0 |
100.00 |
100.00 |
|
|
|
|
|
| u_vendor_test_digest_1 |
66.67 |
66.67 |
|
|
|
|
|
| u_vendor_test_read_lock |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
| u_scrmbl_mtx |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_tlul_adapter_sram |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_err |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_reqfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_rsp_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_rspfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_sram_byte |
0.00 |
0.00 |
|
|
|
|
|
| u_sramreqfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_tlul_data_integ_enc_data |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_tlul_data_integ_enc_instr |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_tlul_lc_gate |
0.00 |
0.00 |
0.00 |
|
0.00 |
0.00 |
|
| gen_lc_gating_muxes[0].u_prim_blanker_d2h |
0.00 |
0.00 |
|
|
|
|
|
| u_blank_and |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_lc_gating_muxes[0].u_prim_blanker_h2d |
0.00 |
0.00 |
|
|
|
|
|
| u_blank_and |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_lc_gating_muxes[1].u_prim_blanker_d2h |
0.00 |
0.00 |
|
|
|
|
|
| u_blank_and |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_lc_gating_muxes[1].u_prim_blanker_h2d |
0.00 |
0.00 |
|
|
|
|
|
| u_blank_and |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_err_en_sync |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_tlul_err_resp |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intg_gen |
0.00 |
0.00 |
|
|
|
|
|
| gen_data_intg.u_tlul_data_integ_enc |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| gen_rsp_intg.u_rsp_gen |
0.00 |
0.00 |
|
|
|
|
|