Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_integ	0.00			0.00
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_cnsty	0.00			0.00
tb.dut.u_otp_ctrl_scrmbl.u_prim_count	0.00			0.00
tb.dut.u_otp_ctrl_dai.u_prim_count	0.00			0.00
tb.dut.u_otp_ctrl_lci.u_prim_count	0.00			0.00
tb.dut.u_otp_ctrl_kdi.u_prim_count_seed	0.00			0.00
tb.dut.u_otp_ctrl_kdi.u_prim_count_entropy	0.00			0.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_count	0.00			0.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_count	0.00			0.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_count	0.00			0.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_count	0.00			0.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_count	0.00			0.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_count	0.00			0.00

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_integ

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_otp_ctrl_lfsr_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_cnsty

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_otp_ctrl_lfsr_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_otp_ctrl_scrmbl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_dai.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_otp_ctrl_dai

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_lci.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_otp_ctrl_lci

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_kdi.u_prim_count_seed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_otp_ctrl_kdi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_kdi.u_prim_count_entropy

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_otp_ctrl_kdi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[7].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[8].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[9].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[10].gen_lifecycle.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=8,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
0.00	0.00

tb.dut.u_otp_ctrl_dai.u_prim_count

	Total	Covered	Percent
Totals	7	0	0.00
Total Bits	42	0	0.00
Total Bits 0->1	21	0	0.00
Total Bits 1->0	21	0	0.00

Ports	7	0	0.00
Port Bits	42	0	0.00
Port Bits 0->1	21	0	0.00
Port Bits 1->0	21	0	0.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	No	No		No		INPUT
rst_ni	No	No		No		INPUT
clr_i	No	No		No		INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	No	No		No		INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[7:0]	No	No		No		OUTPUT
cnt_after_commit_o[7:0]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=2,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
0.00	0.00

tb.dut.u_otp_ctrl_kdi.u_prim_count_seed

SCORE	TOGGLE
0.00	0.00

tb.dut.u_otp_ctrl_kdi.u_prim_count_entropy

	Total	Covered	Percent
Totals	7	0	0.00
Total Bits	18	0	0.00
Total Bits 0->1	9	0	0.00
Total Bits 1->0	9	0	0.00

Ports	7	0	0.00
Port Bits	18	0	0.00
Port Bits 0->1	9	0	0.00
Port Bits 1->0	9	0	0.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	No	No		No		INPUT
rst_ni	No	No		No		INPUT
clr_i	No	No		No		INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	No	No		No		INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[1:0]	No	No		No		OUTPUT
cnt_after_commit_o[1:0]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=3,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
0.00	0.00

tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	0	0.00
Total Bits	22	0	0.00
Total Bits 0->1	11	0	0.00
Total Bits 1->0	11	0	0.00

Ports	7	0	0.00
Port Bits	22	0	0.00
Port Bits 0->1	11	0	0.00
Port Bits 1->0	11	0	0.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	No	No		No		INPUT
rst_ni	No	No		No		INPUT
clr_i	No	No		No		INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	No	No		No		INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[2:0]	No	No		No		OUTPUT
cnt_after_commit_o[2:0]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=40,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
0.00	0.00

tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_integ

SCORE	TOGGLE
0.00	0.00

tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_cnsty

	Total	Covered	Percent
Totals	8	0	0.00
Total Bits	250	0	0.00
Total Bits 0->1	125	0	0.00
Total Bits 1->0	125	0	0.00

Ports	8	0	0.00
Port Bits	250	0	0.00
Port Bits 0->1	125	0	0.00
Port Bits 1->0	125	0	0.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	No	No		No		INPUT
rst_ni	No	No		No		INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	No	No		No		INPUT
set_cnt_i[39:0]	No	No		No		INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	No	No		No		INPUT
step_i[39:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[39:0]	No	No		No		OUTPUT
cnt_after_commit_o[39:0]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=4,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
0.00	0.00

tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_count

SCORE	TOGGLE
0.00	0.00

tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_count

SCORE	TOGGLE
0.00	0.00

tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_count

SCORE	TOGGLE
0.00	0.00

tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	0	0.00
Total Bits	26	0	0.00
Total Bits 0->1	13	0	0.00
Total Bits 1->0	13	0	0.00

Ports	7	0	0.00
Port Bits	26	0	0.00
Port Bits 0->1	13	0	0.00
Port Bits 1->0	13	0	0.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	No	No		No		INPUT
rst_ni	No	No		No		INPUT
clr_i	No	No		No		INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	No	No		No		INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[3:0]	No	No		No		OUTPUT
cnt_after_commit_o[3:0]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=6,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
0.00	0.00

tb.dut.u_otp_ctrl_lci.u_prim_count

	Total	Covered	Percent
Totals	7	0	0.00
Total Bits	34	0	0.00
Total Bits 0->1	17	0	0.00
Total Bits 1->0	17	0	0.00

Ports	7	0	0.00
Port Bits	34	0	0.00
Port Bits 0->1	17	0	0.00
Port Bits 1->0	17	0	0.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	No	No		No		INPUT
rst_ni	No	No		No		INPUT
clr_i	No	No		No		INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	No	No		No		INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[5:0]	No	No		No		OUTPUT
cnt_after_commit_o[5:0]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=5,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
0.00	0.00

tb.dut.u_otp_ctrl_scrmbl.u_prim_count

	Total	Covered	Percent
Totals	7	0	0.00
Total Bits	30	0	0.00
Total Bits 0->1	15	0	0.00
Total Bits 1->0	15	0	0.00

Ports	7	0	0.00
Port Bits	30	0	0.00
Port Bits 0->1	15	0	0.00
Port Bits 1->0	15	0	0.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	No	No		No		INPUT
rst_ni	No	No		No		INPUT
clr_i	No	No		No		INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	No	No		No		INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	No	No		No		OUTPUT
cnt_after_commit_o[4:0]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=1,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
0.00	0.00

tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_count

	Total	Covered	Percent
Totals	7	0	0.00
Total Bits	14	0	0.00
Total Bits 0->1	7	0	0.00
Total Bits 1->0	7	0	0.00

Ports	7	0	0.00
Port Bits	14	0	0.00
Port Bits 0->1	7	0	0.00
Port Bits 1->0	7	0	0.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	No	No		No		INPUT
rst_ni	No	No		No		INPUT
clr_i	No	No		No		INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	No	No		No		INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o	No	No		No		OUTPUT
cnt_after_commit_o	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_integ

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_count_cnsty

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl.u_prim_count

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_dai.u_prim_count

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_lci.u_prim_count

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_kdi.u_prim_count_seed

Toggle Coverage for Instance : tb.dut.u_otp_ctrl_kdi.u_prim_count_entropy

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_count

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_count

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_count

Toggle Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_count

Toggle Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_count

Toggle Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_count