Unified Coverage Report :: Module :: prim_generic_otp

Module : prim_generic_otp

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp.gen_generic.u_impl_generic	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.37	65.13	74.36	94.69	0.00	82.06	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_otp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_dec	0.00	0.00	0.00
u_enc	0.00	0.00
u_prim_ram_1p_adv	0.00	0.00				0.00
u_reg_top	97.15	91.84	99.22	94.69		100.00	100.00
u_state_regs	0.00	0.00				0.00

Line Coverage for Module : prim_generic_otp

	Line No.	Total	Covered	Percent
TOTAL		110	0	0.00
CONT_ASSIGN	76	1	0	0.00
CONT_ASSIGN	80	1	0	0.00
CONT_ASSIGN	84	1	0	0.00
CONT_ASSIGN	86	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	92	1	0	0.00
CONT_ASSIGN	115	1	0	0.00
CONT_ASSIGN	172	1	0	0.00
CONT_ASSIGN	175	1	0	0.00
CONT_ASSIGN	176	1	0	0.00
ALWAYS	180	71	0	0.00
CONT_ASSIGN	329	1	0	0.00
CONT_ASSIGN	349	1	0	0.00
CONT_ASSIGN	353	1	0	0.00
CONT_ASSIGN	358	1	0	0.00
ALWAYS	362	0	0
ALWAYS	362	3	0	0.00
ALWAYS	396	3	0	0.00
ALWAYS	399	19	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' or '../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
76	0	1
80	0	1
84	0	1
86	0	1
89	0	1
92	0	1
115	0	1
172	0	1
175	0	1
176	0	1
180	0	1
181	0	1
182	0	1
183	0	1
184	0	1
185	0	1
186	0	1
187	0	1
188	0	1
189	0	1
190	0	1
191	0	1
193	0	1
196	0	1
197	0	1
198	0	1
199	0	1
200	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
206	0	1
207	0	1
208	0	1
212	0	1
213	0	1
214	0	1
215	0	1
216	0	1
217	0	1
219	0	1
220	0	1
223	0	1
224	0	1
227	0	1
228	0	1
231	0	1
232	0	1
			==> MISSING_ELSE
240	0	1
241	0	1
243	0	1
248	0	1
249	0	1
250	0	1
252	0	1
253	0	1
254	0	1
255	0	1
257	0	1
258	0	1
259	0	1
261	0	1
264	0	1
265	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
273	0	1
274	0	1
277	0	1
283	0	1
284	0	1
285	0	1
287	0	1
288	0	1
289	0	1
291	0	1
			==> MISSING_ELSE
298	0	1
299	0	1
300	0	1
302	0	1
304	0	1
305	0	1
			==> MISSING_ELSE
308	0	1
309	0	1
310	0	1
			==> MISSING_ELSE
315	0	1
329	0	1
349	0	1
353	0	1
358	0	1
362	0	1
363	0	1
365	0	1
396	0	3
399	0	1
400	0	1
401	0	1
402	0	1
403	0	1
404	0	1
405	0	1
406	0	1
407	0	1
409	0	1
410	0	1
411	0	1
412	0	1
413	0	1
414	0	1
415	0	1
416	0	1
			==> MISSING_ELSE
418	0	1
419	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : prim_generic_otp

	Total	Covered	Percent
Conditions	30	0	0.00
Logical	30	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       92
 EXPRESSION (intg_err || fsm_err)
             ----1---    ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       172
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       172
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       199
 EXPRESSION (cmd_i == Init)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       252
 EXPRESSION (rerror[1] && integrity_en_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       257
 EXPRESSION (cnt_q == size_q)
            --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       264
 EXPRESSION (rerror[0] && integrity_en_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       287
 EXPRESSION (cnt_q == size_q)
            --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       308
 EXPRESSION (cnt_q == size_q)
            --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       349
 EXPRESSION (read_ecc_on ? ({{EccWidth {1'b0}}, rdata_corr}) : rdata_ecc)
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       353
 EXPRESSION (write_ecc_on ? ((wdata_ecc | rdata_q[cnt_q])) : (({{EccWidth {1'b0}}, wdata_q[cnt_q]} | rdata_q[cnt_q])))
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       358
 EXPRESSION ((rdata_q[cnt_q] & wdata_ecc) != rdata_q[cnt_q])
            ------------------------1-----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       413
 EXPRESSION (ready_o && valid_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

FSM Coverage for Module : prim_generic_otp

Summary for FSM :: state_q

	Total	Covered	Percent
States	9	0	0.00	(Not included in score)
Transitions	11	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	314	Not Covered
IdleSt	206	Not Covered
InitSt	200	Not Covered
ReadSt	219	Not Covered
ReadWaitSt	240	Not Covered
ResetSt	195	Not Covered
WriteCheckSt	223	Not Covered
WriteSt	289	Not Covered
WriteWaitSt	273	Not Covered

transitions	Line No.	Covered	Tests
IdleSt->ReadSt	219	Not Covered
IdleSt->WriteCheckSt	223	Not Covered
InitSt->IdleSt	206	Not Covered
ReadSt->ReadWaitSt	240	Not Covered
ReadWaitSt->IdleSt	253	Not Covered
ReadWaitSt->ReadSt	261	Not Covered
ResetSt->InitSt	200	Not Covered
WriteCheckSt->WriteWaitSt	273	Not Covered
WriteSt->IdleSt	310	Not Covered
WriteWaitSt->WriteCheckSt	291	Not Covered
WriteWaitSt->WriteSt	289	Not Covered

---

Branch Coverage for Module : prim_generic_otp

	Line No.	Total	Covered	Percent
Branches		41	0	0.00
TERNARY	172	3	0	0.00
TERNARY	349	2	0	0.00
TERNARY	353	2	0	0.00
CASE	193	27	0	0.00
IF	396	2	0	0.00
IF	399	5	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' or '../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	172	(cnt_clr) ? 
-2-:	172	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	349	(read_ecc_on) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	353	(write_ecc_on) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	193	case (state_q)
-2-:	198	if (valid_i)
-3-:	199	if ((cmd_i == Init))
-4-:	214	if (valid_i)
-5-:	217	case (cmd_i)
-6-:	249	if (rvalid)
-7-:	252	if ((rerror[1] && integrity_en_q))
-8-:	257	if ((cnt_q == size_q))
-9-:	264	if ((rerror[0] && integrity_en_q))
-10-:	284	if (rvalid)
-11-:	287	if ((cnt_q == size_q))
-12-:	304	if (wdata_inconsistent)
-13-:	308	if ((cnt_q == size_q))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	1	Read	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	1	Write	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	1	ReadRaw	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	1	WriteRaw	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	1	default	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	-	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	1	1	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	1	0	1	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	1	0	0	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	1	0	-	1	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	1	0	-	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
WriteCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	1	1	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	396	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	399	if ((!rst_ni))
-2-:	413	if ((ready_o && valid_i))
-3-:	418	if (rvalid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	-	Not Covered
0	-	1	Not Covered
0	-	0	Not Covered

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		110	0	0.00
CONT_ASSIGN	76	1	0	0.00
CONT_ASSIGN	80	1	0	0.00
CONT_ASSIGN	84	1	0	0.00
CONT_ASSIGN	86	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	92	1	0	0.00
CONT_ASSIGN	115	1	0	0.00
CONT_ASSIGN	172	1	0	0.00
CONT_ASSIGN	175	1	0	0.00
CONT_ASSIGN	176	1	0	0.00
ALWAYS	180	71	0	0.00
CONT_ASSIGN	329	1	0	0.00
CONT_ASSIGN	349	1	0	0.00
CONT_ASSIGN	353	1	0	0.00
CONT_ASSIGN	358	1	0	0.00
ALWAYS	362	0	0
ALWAYS	362	3	0	0.00
ALWAYS	396	3	0	0.00
ALWAYS	399	19	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' or '../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
76	0	1
80	0	1
84	0	1
86	0	1
89	0	1
92	0	1
115	0	1
172	0	1
175	0	1
176	0	1
180	0	1
181	0	1
182	0	1
183	0	1
184	0	1
185	0	1
186	0	1
187	0	1
188	0	1
189	0	1
190	0	1
191	0	1
193	0	1
196	0	1
197	0	1
198	0	1
199	0	1
200	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
206	0	1
207	0	1
208	0	1
212	0	1
213	0	1
214	0	1
215	0	1
216	0	1
217	0	1
219	0	1
220	0	1
223	0	1
224	0	1
227	0	1
228	0	1
231	0	1
232	0	1
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
240	0	1
241	0	1
243	0	1
248	0	1
249	0	1
250	0	1
252	0	1
253	0	1
254	0	1
255	0	1
257	0	1
258	0	1
259	0	1
261	0	1
264	0	1
265	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
273	0	1
274	0	1
277	0	1
283	0	1
284	0	1
285	0	1
287	0	1
288	0	1
289	0	1
291	0	1
			==> MISSING_ELSE
298	0	1
299	0	1
300	0	1
302	0	1
304	0	1
305	0	1
			==> MISSING_ELSE
308	0	1
309	0	1
310	0	1
			==> MISSING_ELSE
315	0	1
329	0	1
349	0	1
353	0	1
358	0	1
362	0	1
363	0	1
365	0	1
396	0	3
399	0	1
400	0	1
401	0	1
402	0	1
403	0	1
404	0	1
405	0	1
406	0	1
407	0	1
409	0	1
410	0	1
411	0	1
412	0	1
413	0	1
414	0	1
415	0	1
416	0	1
			==> MISSING_ELSE
418	0	1
419	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	29	0	0.00
Logical	29	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       92
 EXPRESSION (intg_err || fsm_err)
             ----1---    ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       172
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       172
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       199
 EXPRESSION (cmd_i == Init)
            -------1-------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Not Covered

 LINE       252
 EXPRESSION (rerror[1] && integrity_en_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       257
 EXPRESSION (cnt_q == size_q)
            --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       264
 EXPRESSION (rerror[0] && integrity_en_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       287
 EXPRESSION (cnt_q == size_q)
            --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       308
 EXPRESSION (cnt_q == size_q)
            --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       349
 EXPRESSION (read_ecc_on ? ({{EccWidth {1'b0}}, rdata_corr}) : rdata_ecc)
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       353
 EXPRESSION (write_ecc_on ? ((wdata_ecc | rdata_q[cnt_q])) : (({{EccWidth {1'b0}}, wdata_q[cnt_q]} | rdata_q[cnt_q])))
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       358
 EXPRESSION ((rdata_q[cnt_q] & wdata_ecc) != rdata_q[cnt_q])
            ------------------------1-----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       413
 EXPRESSION (ready_o && valid_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic

Summary for FSM :: state_q

	Total	Covered	Percent
States	9	0	0.00	(Not included in score)
Transitions	11	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	314	Not Covered
IdleSt	206	Not Covered
InitSt	200	Not Covered
ReadSt	219	Not Covered
ReadWaitSt	240	Not Covered
ResetSt	195	Not Covered
WriteCheckSt	223	Not Covered
WriteSt	289	Not Covered
WriteWaitSt	273	Not Covered

transitions	Line No.	Covered	Tests
IdleSt->ReadSt	219	Not Covered
IdleSt->WriteCheckSt	223	Not Covered
InitSt->IdleSt	206	Not Covered
ReadSt->ReadWaitSt	240	Not Covered
ReadWaitSt->IdleSt	253	Not Covered
ReadWaitSt->ReadSt	261	Not Covered
ResetSt->InitSt	200	Not Covered
WriteCheckSt->WriteWaitSt	273	Not Covered
WriteSt->IdleSt	310	Not Covered
WriteWaitSt->WriteCheckSt	291	Not Covered
WriteWaitSt->WriteSt	289	Not Covered

---

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		39	0	0.00
TERNARY	172	3	0	0.00
TERNARY	349	2	0	0.00
TERNARY	353	2	0	0.00
CASE	193	25	0	0.00
IF	396	2	0	0.00
IF	399	5	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' or '../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	172	(cnt_clr) ? 
-2-:	172	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	349	(read_ecc_on) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	353	(write_ecc_on) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	193	case (state_q)
-2-:	198	if (valid_i)
-3-:	199	if ((cmd_i == Init))
-4-:	214	if (valid_i)
-5-:	217	case (cmd_i)
-6-:	249	if (rvalid)
-7-:	252	if ((rerror[1] && integrity_en_q))
-8-:	257	if ((cnt_q == size_q))
-9-:	264	if ((rerror[0] && integrity_en_q))
-10-:	284	if (rvalid)
-11-:	287	if ((cnt_q == size_q))
-12-:	304	if (wdata_inconsistent)
-13-:	308	if ((cnt_q == size_q))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	1	Read	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	1	Write	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	1	ReadRaw	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	1	WriteRaw	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	1	default	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IdleSt	-	-	0	-	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	1	1	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	1	0	1	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	1	0	0	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	1	0	-	1	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	1	0	-	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
WriteCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	1	1	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
WriteSt	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	396	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	399	if ((!rst_ni))
-2-:	413	if ((ready_o && valid_i))
-3-:	418	if (rvalid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	-	Not Covered
0	-	1	Not Covered
0	-	0	Not Covered