Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	87352305	330501	0	0
check_regwen_rd_A	87352305	1458	0	0
check_timeout_rd_A	87352305	927	0	0
check_trigger_regwen_rd_A	87352305	1470	0	0
consistency_check_period_rd_A	87352305	1455	0	0
creator_sw_cfg_read_lock_rd_A	87352305	933	0	0
direct_access_address_rd_A	87352305	255	0	0
direct_access_wdata_0_rd_A	87352305	26	0	0
direct_access_wdata_1_rd_A	87352305	49	0	0
integrity_check_period_rd_A	87352305	1491	0	0
intr_enable_rd_A	87352305	2034	0	0
owner_sw_cfg_read_lock_rd_A	87352305	915	0	0
rot_creator_auth_codesign_read_lock_rd_A	87352305	949	0	0
rot_creator_auth_state_read_lock_rd_A	87352305	924	0	0
vendor_test_read_lock_rd_A	87352305	825	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87352305	330501	0	0
T14	210552	3894	0	0
T15	0	3201	0	0
T16	0	9688	0	0
T25	0	9641	0	0
T93	0	3475	0	0
T99	0	9628	0	0
T239	0	8865	0	0
T259	19160	0	0	0
T274	0	4824	0	0
T306	0	9070	0	0
T307	0	4013	0	0
T308	27162	0	0	0
T309	53453	0	0	0
T310	45299	0	0	0
T311	39955	0	0	0
T312	8328	0	0	0
T313	55564	0	0	0
T314	26640	0	0	0
T315	42997	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87352305	1458	0	0
T274	246167	10	0	0
T275	0	20	0	0
T294	0	9	0	0
T306	369961	0	0	0
T351	0	6	0	0
T352	0	21	0	0
T353	0	10	0	0
T354	0	19	0	0
T355	0	26	0	0
T356	0	27	0	0
T357	0	15	0	0
T358	4503	0	0	0
T359	69593	0	0	0
T360	34570	0	0	0
T361	33683	0	0	0
T362	30496	0	0	0
T363	24689	0	0	0
T364	12942	0	0	0
T365	47813	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87352305	927	0	0
T274	246167	27	0	0
T275	0	2	0	0
T296	0	1	0	0
T306	369961	0	0	0
T351	0	18	0	0
T352	0	21	0	0
T353	0	15	0	0
T354	0	17	0	0
T355	0	30	0	0
T356	0	21	0	0
T357	0	37	0	0
T358	4503	0	0	0
T359	69593	0	0	0
T360	34570	0	0	0
T361	33683	0	0	0
T362	30496	0	0	0
T363	24689	0	0	0
T364	12942	0	0	0
T365	47813	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87352305	1470	0	0
T274	246167	31	0	0
T275	0	23	0	0
T294	0	14	0	0
T306	369961	0	0	0
T351	0	24	0	0
T352	0	20	0	0
T353	0	11	0	0
T354	0	39	0	0
T355	0	20	0	0
T356	0	17	0	0
T357	0	35	0	0
T358	4503	0	0	0
T359	69593	0	0	0
T360	34570	0	0	0
T361	33683	0	0	0
T362	30496	0	0	0
T363	24689	0	0	0
T364	12942	0	0	0
T365	47813	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87352305	1455	0	0
T274	246167	28	0	0
T294	0	5	0	0
T296	0	7	0	0
T306	369961	0	0	0
T351	0	10	0	0
T352	0	30	0	0
T353	0	23	0	0
T354	0	9	0	0
T355	0	28	0	0
T356	0	20	0	0
T357	0	37	0	0
T358	4503	0	0	0
T359	69593	0	0	0
T360	34570	0	0	0
T361	33683	0	0	0
T362	30496	0	0	0
T363	24689	0	0	0
T364	12942	0	0	0
T365	47813	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87352305	933	0	0
T274	246167	17	0	0
T275	0	26	0	0
T306	369961	0	0	0
T326	0	171	0	0
T351	0	9	0	0
T352	0	35	0	0
T353	0	11	0	0
T354	0	29	0	0
T355	0	18	0	0
T356	0	21	0	0
T357	0	13	0	0
T358	4503	0	0	0
T359	69593	0	0	0
T360	34570	0	0	0
T361	33683	0	0	0
T362	30496	0	0	0
T363	24689	0	0	0
T364	12942	0	0	0
T365	47813	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87352305	255	0	0
T274	246167	23	0	0
T275	0	11	0	0
T296	0	6	0	0
T306	369961	0	0	0
T351	0	5	0	0
T352	0	29	0	0
T353	0	20	0	0
T354	0	20	0	0
T355	0	24	0	0
T356	0	22	0	0
T357	0	31	0	0
T358	4503	0	0	0
T359	69593	0	0	0
T360	34570	0	0	0
T361	33683	0	0	0
T362	30496	0	0	0
T363	24689	0	0	0
T364	12942	0	0	0
T365	47813	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87352305	26	0	0
T161	188022	0	0	0
T352	231692	4	0	0
T353	322348	3	0	0
T354	0	3	0	0
T356	0	8	0	0
T366	0	8	0	0
T367	17579	0	0	0
T368	308272	0	0	0
T369	21807	0	0	0
T370	13087	0	0	0
T371	17817	0	0	0
T372	190208	0	0	0
T373	14799	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87352305	49	0	0
T161	188022	0	0	0
T352	231692	19	0	0
T353	322348	4	0	0
T354	0	9	0	0
T356	0	4	0	0
T357	0	11	0	0
T367	17579	0	0	0
T368	308272	0	0	0
T369	21807	0	0	0
T370	13087	0	0	0
T371	17817	0	0	0
T372	190208	0	0	0
T373	14799	0	0	0
T374	0	2	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87352305	1491	0	0
T274	246167	14	0	0
T275	0	1	0	0
T294	0	1	0	0
T306	369961	0	0	0
T351	0	12	0	0
T352	0	9	0	0
T353	0	11	0	0
T354	0	31	0	0
T355	0	22	0	0
T356	0	31	0	0
T357	0	23	0	0
T358	4503	0	0	0
T359	69593	0	0	0
T360	34570	0	0	0
T361	33683	0	0	0
T362	30496	0	0	0
T363	24689	0	0	0
T364	12942	0	0	0
T365	47813	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87352305	2034	0	0
T71	129298	0	0	0
T102	0	95	0	0
T156	148736	0	0	0
T174	810212	14	0	0
T246	0	30	0	0
T257	21071	0	0	0
T274	0	21	0	0
T275	0	18	0	0
T351	0	38	0	0
T352	0	32	0	0
T353	0	17	0	0
T354	0	28	0	0
T375	0	15	0	0
T376	21588	0	0	0
T377	13019	0	0	0
T378	20786	0	0	0
T379	5580	0	0	0
T380	15016	0	0	0
T381	57088	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87352305	915	0	0
T274	246167	23	0	0
T275	0	18	0	0
T306	369961	0	0	0
T326	0	188	0	0
T351	0	14	0	0
T352	0	32	0	0
T353	0	18	0	0
T354	0	22	0	0
T355	0	11	0	0
T356	0	14	0	0
T357	0	8	0	0
T358	4503	0	0	0
T359	69593	0	0	0
T360	34570	0	0	0
T361	33683	0	0	0
T362	30496	0	0	0
T363	24689	0	0	0
T364	12942	0	0	0
T365	47813	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87352305	949	0	0
T274	246167	22	0	0
T275	0	14	0	0
T296	0	4	0	0
T306	369961	0	0	0
T351	0	3	0	0
T352	0	22	0	0
T353	0	20	0	0
T354	0	33	0	0
T355	0	33	0	0
T356	0	16	0	0
T357	0	27	0	0
T358	4503	0	0	0
T359	69593	0	0	0
T360	34570	0	0	0
T361	33683	0	0	0
T362	30496	0	0	0
T363	24689	0	0	0
T364	12942	0	0	0
T365	47813	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87352305	924	0	0
T274	246167	25	0	0
T275	0	25	0	0
T294	0	8	0	0
T306	369961	0	0	0
T351	0	10	0	0
T352	0	25	0	0
T353	0	4	0	0
T354	0	29	0	0
T355	0	21	0	0
T356	0	16	0	0
T357	0	20	0	0
T358	4503	0	0	0
T359	69593	0	0	0
T360	34570	0	0	0
T361	33683	0	0	0
T362	30496	0	0	0
T363	24689	0	0	0
T364	12942	0	0	0
T365	47813	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87352305	825	0	0
T274	246167	37	0	0
T275	0	12	0	0
T294	0	7	0	0
T296	0	5	0	0
T306	369961	0	0	0
T352	0	8	0	0
T353	0	9	0	0
T354	0	23	0	0
T355	0	27	0	0
T356	0	27	0	0
T357	0	11	0	0
T358	4503	0	0	0
T359	69593	0	0	0
T360	34570	0	0	0
T361	33683	0	0	0
T362	30496	0	0	0
T363	24689	0	0	0
T364	12942	0	0	0
T365	47813	0	0	0