PWRMGR Simulation Results

Wednesday December 20 2023 20:02:55 UTC

GitHub Revision: 9601d3bbdd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30104064247514112511662306974640835321092728874679524971043777466318536599043

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.710s	30.819us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.660s	40.955us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.690s	92.002us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.390s	834.351us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.000s	92.744us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.670s	59.893us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.690s	92.002us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	92.744us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.550s	272.006us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.550s	272.006us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.830s	35.182us	50	50	100.00
		pwrmgr_lowpower_invalid	0.750s	46.769us	50	50	100.00
V2	reset	pwrmgr_reset	1.420s	79.601us	50	50	100.00
		pwrmgr_reset_invalid	1.150s	103.369us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.420s	79.601us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.780s	321.685us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.480s	258.036us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.000s	69.248us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	10.660s	2.176ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.670s	64.074us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.680s	153.146us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.680s	153.146us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.660s	40.955us	5	5	100.00
		pwrmgr_csr_rw	0.690s	92.002us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	92.744us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.960s	43.056us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.660s	40.955us	5	5	100.00
		pwrmgr_csr_rw	0.690s	92.002us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	92.744us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.960s	43.056us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.720s	281.957us	20	20	100.00
		pwrmgr_sec_cm	2.230s	662.057us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.230s	662.057us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.230s	662.057us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.720s	281.957us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.010s	776.827us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.220s	829.614us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.950s	53.331us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.670s	29.424us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.230s	662.057us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.230s	662.057us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.230s	662.057us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.660s	280.159us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	64.159us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.560s	297.577us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.690s	92.002us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.690s	92.002us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.770s	1.145ms	2	50	4.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	43.930s	9.218ms	50	50	100.00
V3		TOTAL			52	100	52.00
		TOTAL			1072	1120	95.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.94	98.22	96.58	99.44	96.00	96.32	100.00	99.02

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 40 failures:
  • Test pwrmgr_escalation_timeout has 40 failures.

    • 0.pwrmgr_escalation_timeout.75333590876135540959295303863070097526098235301690072722705600138295354380300
      Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_escalation_timeout/latest/run.log

        UVM_ERROR @  21066953 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:500
        UVM_INFO @  21066953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.pwrmgr_escalation_timeout.2873814861955698212860099738186592610592209315848731015111747008916680609187
      Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_escalation_timeout/latest/run.log

        UVM_ERROR @  21132538 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:500
        UVM_INFO @  21132538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 38 more failures.

• UVM_FATAL (pwrmgr_escalation_timeout_vseq.sv:30) [pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable has 8 failures:
  • Test pwrmgr_escalation_timeout has 8 failures.

    • 16.pwrmgr_escalation_timeout.30740214914901137528959783108931187434116905982526526989992174868454469106829
      Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_escalation_timeout/latest/run.log

        UVM_FATAL @ 469494247 ps: (pwrmgr_escalation_timeout_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
        UVM_INFO @ 469494247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 24.pwrmgr_escalation_timeout.88191112952723418615678879742033998962620843895174786014836370513395063733259
      Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_escalation_timeout/latest/run.log

        UVM_FATAL @ 246583686 ps: (pwrmgr_escalation_timeout_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
        UVM_INFO @ 246583686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

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