Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T10

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	25251541	6190	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	25251541	260895	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	25251541	10561764	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	25251541	260905	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	25251541	6190	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	25251541	260895	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	25251541	10561764	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	25251541	260905	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	6190	0	0
T3	29342	24	0	0
T4	9934	0	0	0
T5	279157	128	0	0
T6	1906	1	0	0
T7	17132	0	0	0
T8	1080	0	0	0
T9	3701	0	0	0
T10	3292	1	0	0
T14	6699	0	0	0
T21	0	73	0	0
T23	0	22	0	0
T33	25277	19	0	0
T42	0	3	0	0
T70	0	13	0	0
T71	0	26	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	260895	0	0
T3	29342	843	0	0
T4	9934	0	0	0
T5	279157	2470	0	0
T6	1906	85	0	0
T7	17132	0	0	0
T8	1080	0	0	0
T9	3701	0	0	0
T10	3292	210	0	0
T14	6699	0	0	0
T21	0	3573	0	0
T23	0	1207	0	0
T33	25277	524	0	0
T42	0	676	0	0
T70	0	925	0	0
T71	0	525	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	10561764	0	0
T1	1862	912	0	0
T2	4018	0	0	0
T3	29342	17240	0	0
T4	9934	5858	0	0
T5	279157	111090	0	0
T6	1906	92	0	0
T7	17132	9878	0	0
T8	1080	829	0	0
T9	3701	1298	0	0
T10	3292	142	0	0
T33	0	12149	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	260905	0	0
T3	29342	843	0	0
T4	9934	0	0	0
T5	279157	2470	0	0
T6	1906	85	0	0
T7	17132	0	0	0
T8	1080	0	0	0
T9	3701	0	0	0
T10	3292	210	0	0
T14	6699	0	0	0
T21	0	3576	0	0
T23	0	1207	0	0
T33	25277	524	0	0
T42	0	676	0	0
T70	0	925	0	0
T71	0	525	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	6190	0	0
T3	29342	24	0	0
T4	9934	0	0	0
T5	279157	128	0	0
T6	1906	1	0	0
T7	17132	0	0	0
T8	1080	0	0	0
T9	3701	0	0	0
T10	3292	1	0	0
T14	6699	0	0	0
T21	0	73	0	0
T23	0	22	0	0
T33	25277	19	0	0
T42	0	3	0	0
T70	0	13	0	0
T71	0	26	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	260895	0	0
T3	29342	843	0	0
T4	9934	0	0	0
T5	279157	2470	0	0
T6	1906	85	0	0
T7	17132	0	0	0
T8	1080	0	0	0
T9	3701	0	0	0
T10	3292	210	0	0
T14	6699	0	0	0
T21	0	3573	0	0
T23	0	1207	0	0
T33	25277	524	0	0
T42	0	676	0	0
T70	0	925	0	0
T71	0	525	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	10561764	0	0
T1	1862	912	0	0
T2	4018	0	0	0
T3	29342	17240	0	0
T4	9934	5858	0	0
T5	279157	111090	0	0
T6	1906	92	0	0
T7	17132	9878	0	0
T8	1080	829	0	0
T9	3701	1298	0	0
T10	3292	142	0	0
T33	0	12149	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	260905	0	0
T3	29342	843	0	0
T4	9934	0	0	0
T5	279157	2470	0	0
T6	1906	85	0	0
T7	17132	0	0	0
T8	1080	0	0	0
T9	3701	0	0	0
T10	3292	210	0	0
T14	6699	0	0	0
T21	0	3576	0	0
T23	0	1207	0	0
T33	25277	524	0	0
T42	0	676	0	0
T70	0	925	0	0
T71	0	525	0	0