Unified Coverage Report :: Module :: pwrmgr

Module : pwrmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.51	100.00	83.33	99.21		100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_0.1/rtl/pwrmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	96.51	100.00	83.33	99.21		100.00	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.51	100.00	83.33	99.21		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.76	98.22	96.58	99.44	96.00	96.32	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
clkmgr_pwrmgr_sva_if	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
i_wake_info	100.00	100.00	100.00			100.00
intr_wakeup	93.75	100.00	75.00			100.00	100.00
pwrmgr_clock_enables_sva_if	100.00	100.00	100.00				100.00
pwrmgr_csr_assert	100.00						100.00
pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00
pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_cdc	100.00	100.00	100.00			100.00	100.00
u_esc_clk_buf	100.00	100.00
u_esc_rst_buf	100.00	100.00
u_esc_rx	98.21			98.21
u_esc_timeout	92.79	100.00	75.00			96.15	100.00
u_fsm	98.66	100.00	98.44		94.87	100.00	100.00
u_ndm_sync	100.00	100.00				100.00
u_prim_lc_sync_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_hw_debug_en	100.00	100.00				100.00	100.00
u_reg	97.24	96.01	97.64	100.00		92.53	100.00
u_slow_fsm	99.41	100.00	97.06		100.00	100.00	100.00
u_sw_req_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr

	Line No.	Total	Covered	Percent
TOTAL		42	42	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
ALWAYS	178	4	4	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	227	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
ALWAYS	319	6	6	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	359	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	633	1	1	100.00
CONT_ASSIGN	637	1	1	100.00
CONT_ASSIGN	694	0	0
ALWAYS	698	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_0.1/rtl/pwrmgr.sv' or '../src/lowrisc_ip_pwrmgr_0.1/rtl/pwrmgr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
108	1	1
116	1	1
117	1	1
178	1	1
179	1	1
180	1	1
182	1	1
			MISSING_ELSE
209	1	1
210	1	1
211	1	1
213	1	1
214	1	1
227	1	1
316	1	1
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
			MISSING_ELSE
328	1	1
330	1	1
332	1	1
339	1	1
340	1	1
354	1	1
359	1	1
457	1	1
482	1	1
486	1	1
494	6	6
499	2	2
503	1	1
560	1	1
633	1	1
637	1	1
694		unreachable
698		unreachable
699		unreachable
701		unreachable

---

Cond Coverage for Module : pwrmgr

	Total	Covered	Percent
Conditions	30	25	83.33
Logical	30	25	83.33
Non-Logical	0	0
Event	0	0

 LINE       213
 EXPRESSION (esc_rst_req_q | esc_timeout)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable	T11,T12,T13
1	0	Covered	T2,T5,T14

 LINE       321
 EXPRESSION (((!lowpwr_cfg_wen)) && (clr_cfg_lock || wkup))
             ---------1---------    -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       321
 SUB-EXPRESSION (clr_cfg_lock || wkup)
                 ------1-----    --2-

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T2,T3

 LINE       340
 EXPRESSION (peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx] | reg2hw.fault_status.main_pd_glitch.q)
             ----------------------------1----------------------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T2,T3,T5

 LINE       354
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       359
 EXPRESSION (reg2hw.fault_status.reg_intg_err.q | reg2hw.fault_status.esc_timeout.q | reg2hw.fault_status.main_pd_glitch.q)
             -----------------1----------------   ----------------2----------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	1	0	Covered	T11,T12,T13
1	0	0	Covered	T18,T19,T20

 LINE       383
 EXPRESSION (reg2hw.cfg_cdc_sync.qe & reg2hw.cfg_cdc_sync.q)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       560
 EXPRESSION (reg2hw.control.low_power_hint.q == LowPower)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       562
 EXPRESSION (core_sleeping & low_power_hint)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       633
 EXPRESSION (reg2hw.wake_info.abort.qe | reg2hw.wake_info.fall_through.qe | reg2hw.wake_info.reasons.qe)
             ------------1------------   ----------------2---------------   -------------3-------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

---

Toggle Coverage for Module : pwrmgr

	Total	Covered	Percent
Totals	81	79	97.53
Total Bits	508	504	99.21
Total Bits 0->1	254	252	99.21
Total Bits 1->0	254	252	99.21

Ports	81	79	97.53
Port Bits	508	504	99.21
Port Bits 0->1	254	252	99.21
Port Bits 1->0	254	252	99.21

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_slow_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_slow_ni	Yes	Yes	T5,T6,T10	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T5,T6,T10	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
clk_lc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_lc_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T5,T21,T22	Yes	T5,T21,T22	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
pwr_ast_i.main_pok	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
pwr_ast_i.usb_clk_val	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
pwr_ast_i.io_clk_val	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
pwr_ast_i.core_clk_val	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
pwr_ast_i.slow_clk_val	No	No		No		INPUT
pwr_ast_o.usb_clk_en	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.io_clk_en	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.core_clk_en	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.slow_clk_en	No	No		No		OUTPUT
pwr_ast_o.pwr_clamp	Yes	Yes	T1,T2,T3	Yes	T3,T4,T5	OUTPUT
pwr_ast_o.pwr_clamp_env	Yes	Yes	T1,T2,T3	Yes	T3,T4,T5	OUTPUT
pwr_ast_o.main_pd_n	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
pwr_rst_i.rst_sys_src_n[1:0]	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
pwr_rst_i.rst_lc_src_n[1:0]	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
pwr_rst_o.reset_cause[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_rst_o.rstreqs[4:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
pwr_rst_o.rst_sys_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T5	OUTPUT
pwr_rst_o.rst_lc_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T5	OUTPUT
pwr_clk_o.usb_ip_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_clk_o.io_ip_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_clk_o.main_ip_clk_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_clk_i.usb_status	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_clk_i.io_status	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_clk_i.main_status	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_otp_i.otp_idle	Yes	Yes	T1,T5,T21	Yes	T1,T3,T4	INPUT
pwr_otp_i.otp_done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_otp_o.otp_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_lc_i.lc_idle	Yes	Yes	T1,T5,T8	Yes	T1,T3,T4	INPUT
pwr_lc_i.lc_done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_lc_o.lc_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_flash_i.flash_idle	Yes	Yes	T1,T5,T21	Yes	T1,T3,T4	INPUT
pwr_cpu_i.core_sleeping	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
fetch_en_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T2,T3,T23	Yes	T2,T3,T23	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T2,T3,T23	Yes	T2,T3,T23	INPUT
wakeups_i[5:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
rstreqs_i[1:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
ndmreset_req_i	Yes	Yes	T2,T5,T14	Yes	T2,T5,T14	INPUT
strap_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
low_power_o	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	OUTPUT
rom_ctrl_i.good[3:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
rom_ctrl_i.done[3:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
sw_rst_req_i[3:0]	Yes	Yes	T2,T5,T14	Yes	T2,T5,T14	INPUT
esc_rst_tx_i.esc_n	Yes	Yes	T2,T5,T14	Yes	T2,T5,T14	INPUT
esc_rst_tx_i.esc_p	Yes	Yes	T2,T5,T14	Yes	T2,T5,T14	INPUT
esc_rst_rx_o.resp_n	Yes	Yes	T2,T5,T14	Yes	T2,T5,T14	OUTPUT
esc_rst_rx_o.resp_p	Yes	Yes	T2,T5,T14	Yes	T2,T5,T14	OUTPUT
intr_wakeup_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : pwrmgr

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
IF	178	3	3	100.00
IF	319	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_0.1/rtl/pwrmgr.sv' or '../src/lowrisc_ip_pwrmgr_0.1/rtl/pwrmgr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	178	if ((!rst_lc_n))
-2-:	180	if (esc_rst_req_d)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T5,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	319	if ((!rst_ni))
-2-:	321	if (((!lowpwr_cfg_wen) && (clr_cfg_lock || wkup)))
-3-:	323	if (low_power_hint)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	18	18	100.00	18	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	18	18	100.00	18	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertNumCheck_A	905	905	0	0
AlertsKnownO_A	25251541	24729561	0	0
AstKnownO_A	25251541	24729561	0	0
ClkKnownO_A	25251541	24729561	0	0
ClkRatio_A	25251541	24729561	0	0
FpvSecCmFsmCheck_A	25251541	60	0	0
FpvSecCmRegWeOnehotCheck_A	25251541	60	0	0
FpvSecCmSlowFsmCheck_A	4984580	60	0	0
GlitchStatusPersist_A	25251541	6462	0	0
IntrKnownO_A	25251541	24729561	0	0
LcKnownO_A	25251541	24729561	0	0
OtpKnownO_A	25251541	24729561	0	0
PwrmgrSecCmEscToLCReset_A	25251541	2287	0	0
PwrmgrSecCmEscToSlowResetReq_A	4984580	15188	0	0
PwrmgrSecCmFsmEscToResetReq_A	25251541	100398	0	0
RstKnownO_A	25251541	24729561	0	0
TlAReadyKnownO_A	25251541	24729561	0	0
TlDValidKnownO_A	25251541	24729561	0	0

AlertNumCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

AlertsKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	24729561	0	0
T1	1862	1784	0	0
T2	4018	3961	0	0
T3	29342	29283	0	0
T4	9934	9855	0	0
T5	279157	269481	0	0
T6	1906	1572	0	0
T7	17132	17065	0	0
T8	1080	993	0	0
T9	3701	3611	0	0
T10	3292	2906	0	0

AstKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	24729561	0	0
T1	1862	1784	0	0
T2	4018	3961	0	0
T3	29342	29283	0	0
T4	9934	9855	0	0
T5	279157	269481	0	0
T6	1906	1572	0	0
T7	17132	17065	0	0
T8	1080	993	0	0
T9	3701	3611	0	0
T10	3292	2906	0	0

ClkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	24729561	0	0
T1	1862	1784	0	0
T2	4018	3961	0	0
T3	29342	29283	0	0
T4	9934	9855	0	0
T5	279157	269481	0	0
T6	1906	1572	0	0
T7	17132	17065	0	0
T8	1080	993	0	0
T9	3701	3611	0	0
T10	3292	2906	0	0

ClkRatio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	24729561	0	0
T1	1862	1784	0	0
T2	4018	3961	0	0
T3	29342	29283	0	0
T4	9934	9855	0	0
T5	279157	269481	0	0
T6	1906	1572	0	0
T7	17132	17065	0	0
T8	1080	993	0	0
T9	3701	3611	0	0
T10	3292	2906	0	0

FpvSecCmFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	60	0	0
T17	2557	0	0	0
T18	21280	10	0	0
T19	25148	20	0	0
T20	0	10	0	0
T24	0	10	0	0
T25	0	10	0	0
T26	1848	0	0	0
T27	6427	0	0	0
T28	6472	0	0	0
T29	64212	0	0	0
T30	4283	0	0	0
T31	5097	0	0	0
T32	979	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	60	0	0
T17	2557	0	0	0
T18	21280	10	0	0
T19	25148	20	0	0
T20	0	10	0	0
T24	0	10	0	0
T25	0	10	0	0
T26	1848	0	0	0
T27	6427	0	0	0
T28	6472	0	0	0
T29	64212	0	0	0
T30	4283	0	0	0
T31	5097	0	0	0
T32	979	0	0	0

FpvSecCmSlowFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4984580	60	0	0
T17	233	0	0	0
T18	2144	10	0	0
T19	5040	20	0	0
T20	0	10	0	0
T24	0	10	0	0
T25	0	10	0	0
T26	165	0	0	0
T27	662	0	0	0
T28	740	0	0	0
T29	6387	0	0	0
T30	1268	0	0	0
T31	759	0	0	0
T32	390	0	0	0

GlitchStatusPersist_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	6462	0	0
T2	4018	2	0	0
T3	29342	15	0	0
T4	9934	0	0	0
T5	279157	171	0	0
T6	1906	0	0	0
T7	17132	0	0	0
T8	1080	0	0	0
T9	3701	0	0	0
T10	3292	0	0	0
T14	6699	1	0	0
T21	0	121	0	0
T23	0	11	0	0
T33	0	15	0	0
T34	0	4	0	0
T35	0	1	0	0
T36	0	1	0	0

IntrKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	24729561	0	0
T1	1862	1784	0	0
T2	4018	3961	0	0
T3	29342	29283	0	0
T4	9934	9855	0	0
T5	279157	269481	0	0
T6	1906	1572	0	0
T7	17132	17065	0	0
T8	1080	993	0	0
T9	3701	3611	0	0
T10	3292	2906	0	0

LcKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	24729561	0	0
T1	1862	1784	0	0
T2	4018	3961	0	0
T3	29342	29283	0	0
T4	9934	9855	0	0
T5	279157	269481	0	0
T6	1906	1572	0	0
T7	17132	17065	0	0
T8	1080	993	0	0
T9	3701	3611	0	0
T10	3292	2906	0	0

OtpKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	24729561	0	0
T1	1862	1784	0	0
T2	4018	3961	0	0
T3	29342	29283	0	0
T4	9934	9855	0	0
T5	279157	269481	0	0
T6	1906	1572	0	0
T7	17132	17065	0	0
T8	1080	993	0	0
T9	3701	3611	0	0
T10	3292	2906	0	0

PwrmgrSecCmEscToLCReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	2287	0	0
T2	4018	3	0	0
T3	29342	0	0	0
T4	9934	0	0	0
T5	279157	48	0	0
T6	1906	0	0	0
T7	17132	0	0	0
T8	1080	0	0	0
T9	3701	0	0	0
T10	3292	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	6699	4	0	0
T21	0	48	0	0
T35	0	2	0	0
T36	0	4	0	0
T37	0	2	0	0
T38	0	1	0	0

PwrmgrSecCmEscToSlowResetReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4984580	15188	0	0
T2	304	7	0	0
T3	5870	0	0	0
T4	984	0	0	0
T5	219717	1114	0	0
T6	364	0	0	0
T7	1732	0	0	0
T8	414	0	0	0
T9	1968	0	0	0
T10	312	0	0	0
T14	671	11	0	0
T21	0	259	0	0
T34	0	3	0	0
T35	0	9	0	0
T36	0	10	0	0
T37	0	6	0	0
T38	0	8	0	0
T39	0	3	0	0

PwrmgrSecCmFsmEscToResetReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	100398	0	0
T2	4018	112	0	0
T3	29342	0	0	0
T4	9934	0	0	0
T5	279157	1609	0	0
T6	1906	0	0	0
T7	17132	0	0	0
T8	1080	0	0	0
T9	3701	0	0	0
T10	3292	0	0	0
T11	0	16	0	0
T14	6699	103	0	0
T21	0	3235	0	0
T34	0	21	0	0
T35	0	28	0	0
T36	0	84	0	0
T37	0	81	0	0
T39	0	13	0	0

RstKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	24729561	0	0
T1	1862	1784	0	0
T2	4018	3961	0	0
T3	29342	29283	0	0
T4	9934	9855	0	0
T5	279157	269481	0	0
T6	1906	1572	0	0
T7	17132	17065	0	0
T8	1080	993	0	0
T9	3701	3611	0	0
T10	3292	2906	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	24729561	0	0
T1	1862	1784	0	0
T2	4018	3961	0	0
T3	29342	29283	0	0
T4	9934	9855	0	0
T5	279157	269481	0	0
T6	1906	1572	0	0
T7	17132	17065	0	0
T8	1080	993	0	0
T9	3701	3611	0	0
T10	3292	2906	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	24729561	0	0
T1	1862	1784	0	0
T2	4018	3961	0	0
T3	29342	29283	0	0
T4	9934	9855	0	0
T5	279157	269481	0	0
T6	1906	1572	0	0
T7	17132	17065	0	0
T8	1080	993	0	0
T9	3701	3611	0	0
T10	3292	2906	0	0