Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25862475	16324	0	0
intr_enable_rd_A	25862475	46286	0	0
reset_en_rd_A	25862475	1423	0	0
reset_en_regwen_rd_A	25862475	1266	0	0
wake_info_capture_dis_rd_A	25862475	1286	0	0
wakeup_en_rd_A	25862475	1965	0	0
wakeup_en_regwen_rd_A	25862475	1366	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25862475	16324	0	0
T5	279157	2	0	0
T6	1906	0	0	0
T7	17132	0	0	0
T8	1080	0	0	0
T9	3701	0	0	0
T10	3292	0	0	0
T14	6699	0	0	0
T21	0	19	0	0
T22	0	16	0	0
T33	25277	0	0	0
T43	0	28	0	0
T44	0	429	0	0
T45	0	118	0	0
T72	6455	0	0	0
T73	7769	0	0	0
T75	0	39	0	0
T83	0	4	0	0
T116	0	20	0	0
T117	0	33	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25862475	46286	0	0
T7	17132	26	0	0
T8	1080	0	0	0
T9	3701	0	0	0
T10	3292	0	0	0
T11	889	0	0	0
T14	6699	0	0	0
T22	0	1840	0	0
T23	0	203	0	0
T33	25277	68	0	0
T34	0	13	0	0
T35	0	23	0	0
T50	0	17	0	0
T72	6455	0	0	0
T73	7769	0	0	0
T74	7223	0	0	0
T78	0	14	0	0
T118	0	19	0	0
T119	0	21	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25862475	1423	0	0
T13	2424	0	0	0
T22	413703	8	0	0
T41	3241	0	0	0
T49	0	49	0	0
T54	0	17	0	0
T58	0	22	0	0
T68	0	57	0	0
T75	0	5	0	0
T76	9995	0	0	0
T77	31619	0	0	0
T78	5893	0	0	0
T79	2583	0	0	0
T80	4316	0	0	0
T81	1019	0	0	0
T82	1351	0	0	0
T83	0	5	0	0
T88	0	26	0	0
T95	0	19	0	0
T120	0	15	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25862475	1266	0	0
T13	2424	0	0	0
T22	413703	5	0	0
T41	3241	0	0	0
T49	0	11	0	0
T54	0	3	0	0
T58	0	7	0	0
T68	0	42	0	0
T75	0	21	0	0
T76	9995	0	0	0
T77	31619	0	0	0
T78	5893	0	0	0
T79	2583	0	0	0
T80	4316	0	0	0
T81	1019	0	0	0
T82	1351	0	0	0
T83	0	11	0	0
T88	0	2	0	0
T95	0	25	0	0
T120	0	26	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25862475	1286	0	0
T49	20468	19	0	0
T54	1690	2	0	0
T58	0	12	0	0
T64	5078	0	0	0
T68	8433	50	0	0
T75	522570	13	0	0
T83	401312	4	0	0
T85	5124	0	0	0
T86	89149	0	0	0
T87	1633	0	0	0
T88	0	11	0	0
T95	0	38	0	0
T98	0	6	0	0
T120	0	19	0	0
T121	1186	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25862475	1965	0	0
T49	20468	86	0	0
T54	1690	20	0	0
T58	0	10	0	0
T64	5078	0	0	0
T68	8433	166	0	0
T75	522570	9	0	0
T83	401312	3	0	0
T85	5124	0	0	0
T86	89149	0	0	0
T87	1633	0	0	0
T88	0	4	0	0
T95	0	32	0	0
T98	0	21	0	0
T120	0	33	0	0
T121	1186	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25862475	1366	0	0
T49	20468	19	0	0
T54	1690	9	0	0
T58	0	1	0	0
T64	5078	0	0	0
T68	8433	53	0	0
T75	522570	4	0	0
T83	401312	5	0	0
T85	5124	0	0	0
T86	89149	0	0	0
T87	1633	0	0	0
T88	0	6	0	0
T95	0	29	0	0
T98	0	9	0	0
T120	0	11	0	0
T121	1186	0	0	0