Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	25251541	60521	0	0
RomAllowCheckGoodState_A	25251541	60572	0	0
RomBlockActiveState_A	25251541	30447	0	0
RomBlockCheckGoodState_A	25251541	433020	0	0
RomIntgChkDisFalse_A	25251541	24630772	0	0
RomIntgChkDisTrue_A	25251541	98789	0	0
RstreqChkEsctimeout_A	25251541	4522	0	0
RstreqChkFsmterm_A	25251541	120	0	0
RstreqChkGlbesc_A	25251541	4524	0	0
RstreqChkMainpd_A	25251541	1052062	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	60521	0	0
T1	1862	13	0	0
T2	4018	8	0	0
T3	29342	82	0	0
T4	9934	10	0	0
T5	279157	1323	0	0
T6	1906	5	0	0
T7	17132	17	0	0
T8	1080	2	0	0
T9	3701	12	0	0
T10	3292	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	60572	0	0
T1	1862	13	0	0
T2	4018	8	0	0
T3	29342	82	0	0
T4	9934	10	0	0
T5	279157	1323	0	0
T6	1906	5	0	0
T7	17132	17	0	0
T8	1080	2	0	0
T9	3701	12	0	0
T10	3292	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	30447	0	0
T2	4018	448	0	0
T3	29342	0	0	0
T4	9934	0	0	0
T5	279157	0	0	0
T6	1906	0	0	0
T7	17132	0	0	0
T8	1080	0	0	0
T9	3701	0	0	0
T10	3292	0	0	0
T14	6699	0	0	0
T34	0	712	0	0
T35	0	197	0	0
T36	0	447	0	0
T37	0	881	0	0
T71	0	1	0	0
T78	0	1240	0	0
T118	0	151	0	0
T119	0	33	0	0
T122	0	1091	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	433020	0	0
T2	4018	420	0	0
T3	29342	2197	0	0
T4	9934	0	0	0
T5	279157	5184	0	0
T6	1906	0	0	0
T7	17132	0	0	0
T8	1080	0	0	0
T9	3701	0	0	0
T10	3292	0	0	0
T14	6699	0	0	0
T21	0	2596	0	0
T23	0	4051	0	0
T33	0	1331	0	0
T34	0	422	0	0
T35	0	63	0	0
T36	0	425	0	0
T37	0	1024	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	24630772	0	0
T1	1862	1784	0	0
T2	4018	3590	0	0
T3	29342	28781	0	0
T4	9934	9855	0	0
T5	279157	269481	0	0
T6	1906	1572	0	0
T7	17132	17065	0	0
T8	1080	993	0	0
T9	3701	3611	0	0
T10	3292	2906	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	98789	0	0
T2	4018	371	0	0
T3	29342	502	0	0
T4	9934	0	0	0
T5	279157	0	0	0
T6	1906	0	0	0
T7	17132	0	0	0
T8	1080	0	0	0
T9	3701	0	0	0
T10	3292	0	0	0
T14	6699	0	0	0
T23	0	2273	0	0
T34	0	246	0	0
T35	0	541	0	0
T37	0	2238	0	0
T71	0	140	0	0
T78	0	260	0	0
T118	0	83	0	0
T119	0	76	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	4522	0	0
T2	4018	3	0	0
T3	29342	0	0	0
T4	9934	0	0	0
T5	279157	141	0	0
T6	1906	0	0	0
T7	17132	0	0	0
T8	1080	0	0	0
T9	3701	0	0	0
T10	3292	0	0	0
T11	0	1	0	0
T14	6699	4	0	0
T21	0	102	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	4	0	0
T37	0	2	0	0
T39	0	5	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	120	0	0
T17	2557	0	0	0
T18	21280	20	0	0
T19	25148	40	0	0
T20	0	20	0	0
T24	0	20	0	0
T25	0	20	0	0
T26	1848	0	0	0
T27	6427	0	0	0
T28	6472	0	0	0
T29	64212	0	0	0
T30	4283	0	0	0
T31	5097	0	0	0
T32	979	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	4524	0	0
T2	4018	3	0	0
T3	29342	0	0	0
T4	9934	0	0	0
T5	279157	141	0	0
T6	1906	0	0	0
T7	17132	0	0	0
T8	1080	0	0	0
T9	3701	0	0	0
T10	3292	0	0	0
T11	0	1	0	0
T14	6699	4	0	0
T21	0	102	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	4	0	0
T37	0	2	0	0
T39	0	5	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25251541	1052062	0	0
T2	4018	693	0	0
T3	29342	3752	0	0
T4	9934	0	0	0
T5	279157	6911	0	0
T6	1906	0	0	0
T7	17132	0	0	0
T8	1080	0	0	0
T9	3701	0	0	0
T10	3292	0	0	0
T14	6699	18	0	0
T21	0	20040	0	0
T23	0	4702	0	0
T33	0	2076	0	0
T34	0	866	0	0
T35	0	63	0	0
T36	0	364	0	0