Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5622 |
1 |
|
|
T1 |
28 |
|
T3 |
6 |
|
T5 |
6 |
auto[1] |
16250 |
1 |
|
|
T1 |
51 |
|
T2 |
13 |
|
T3 |
4 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9845 |
1 |
|
|
T1 |
38 |
|
T2 |
5 |
|
T3 |
6 |
auto[1] |
12027 |
1 |
|
|
T1 |
41 |
|
T2 |
8 |
|
T3 |
4 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10700 |
1 |
|
|
T1 |
38 |
|
T2 |
5 |
|
T3 |
5 |
auto[1] |
11172 |
1 |
|
|
T1 |
41 |
|
T2 |
8 |
|
T3 |
5 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1429 |
1 |
|
|
T1 |
6 |
|
T3 |
3 |
|
T5 |
2 |
auto[0] |
auto[0] |
auto[1] |
1201 |
1 |
|
|
T1 |
9 |
|
T3 |
2 |
|
T8 |
3 |
auto[0] |
auto[1] |
auto[0] |
3792 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T7 |
14 |
auto[0] |
auto[1] |
auto[1] |
3423 |
1 |
|
|
T1 |
10 |
|
T2 |
3 |
|
T3 |
1 |
auto[1] |
auto[0] |
auto[0] |
1340 |
1 |
|
|
T1 |
8 |
|
T5 |
1 |
|
T8 |
1 |
auto[1] |
auto[0] |
auto[1] |
1652 |
1 |
|
|
T1 |
5 |
|
T3 |
1 |
|
T5 |
3 |
auto[1] |
auto[1] |
auto[0] |
4139 |
1 |
|
|
T1 |
11 |
|
T2 |
3 |
|
T3 |
2 |
auto[1] |
auto[1] |
auto[1] |
4896 |
1 |
|
|
T1 |
17 |
|
T2 |
5 |
|
T3 |
1 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5622 |
1 |
|
|
T1 |
28 |
|
T3 |
6 |
|
T5 |
6 |
auto[1] |
16250 |
1 |
|
|
T1 |
51 |
|
T2 |
13 |
|
T3 |
4 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9904 |
1 |
|
|
T1 |
36 |
|
T2 |
7 |
|
T3 |
8 |
auto[1] |
11968 |
1 |
|
|
T1 |
43 |
|
T2 |
6 |
|
T3 |
2 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10797 |
1 |
|
|
T1 |
40 |
|
T2 |
9 |
|
T3 |
5 |
auto[1] |
11075 |
1 |
|
|
T1 |
39 |
|
T2 |
4 |
|
T3 |
5 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1384 |
1 |
|
|
T1 |
8 |
|
T3 |
3 |
|
T5 |
2 |
auto[0] |
auto[0] |
auto[1] |
1194 |
1 |
|
|
T1 |
5 |
|
T3 |
2 |
|
T5 |
2 |
auto[0] |
auto[1] |
auto[0] |
3894 |
1 |
|
|
T1 |
14 |
|
T2 |
5 |
|
T3 |
2 |
auto[0] |
auto[1] |
auto[1] |
3432 |
1 |
|
|
T1 |
9 |
|
T2 |
2 |
|
T3 |
1 |
auto[1] |
auto[0] |
auto[0] |
1422 |
1 |
|
|
T1 |
5 |
|
T5 |
1 |
|
T8 |
3 |
auto[1] |
auto[0] |
auto[1] |
1622 |
1 |
|
|
T1 |
10 |
|
T3 |
1 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[0] |
4097 |
1 |
|
|
T1 |
13 |
|
T2 |
4 |
|
T6 |
1 |
auto[1] |
auto[1] |
auto[1] |
4827 |
1 |
|
|
T1 |
15 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5622 |
1 |
|
|
T1 |
28 |
|
T3 |
6 |
|
T5 |
6 |
auto[1] |
16250 |
1 |
|
|
T1 |
51 |
|
T2 |
13 |
|
T3 |
4 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9830 |
1 |
|
|
T1 |
41 |
|
T2 |
3 |
|
T3 |
4 |
auto[1] |
12042 |
1 |
|
|
T1 |
38 |
|
T2 |
10 |
|
T3 |
6 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10816 |
1 |
|
|
T1 |
41 |
|
T2 |
9 |
|
T3 |
5 |
auto[1] |
11056 |
1 |
|
|
T1 |
38 |
|
T2 |
4 |
|
T3 |
5 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1367 |
1 |
|
|
T1 |
8 |
|
T3 |
1 |
|
T5 |
1 |
auto[0] |
auto[0] |
auto[1] |
1164 |
1 |
|
|
T1 |
5 |
|
T3 |
1 |
|
T5 |
4 |
auto[0] |
auto[1] |
auto[0] |
3959 |
1 |
|
|
T1 |
14 |
|
T2 |
2 |
|
T3 |
2 |
auto[0] |
auto[1] |
auto[1] |
3340 |
1 |
|
|
T1 |
14 |
|
T2 |
1 |
|
T5 |
1 |
auto[1] |
auto[0] |
auto[0] |
1412 |
1 |
|
|
T1 |
6 |
|
T3 |
2 |
|
T8 |
3 |
auto[1] |
auto[0] |
auto[1] |
1679 |
1 |
|
|
T1 |
9 |
|
T3 |
2 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[0] |
4078 |
1 |
|
|
T1 |
13 |
|
T2 |
7 |
|
T5 |
2 |
auto[1] |
auto[1] |
auto[1] |
4873 |
1 |
|
|
T1 |
10 |
|
T2 |
3 |
|
T3 |
2 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5622 |
1 |
|
|
T1 |
28 |
|
T3 |
6 |
|
T5 |
6 |
auto[1] |
16250 |
1 |
|
|
T1 |
51 |
|
T2 |
13 |
|
T3 |
4 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9796 |
1 |
|
|
T1 |
28 |
|
T2 |
4 |
|
T3 |
1 |
auto[1] |
12076 |
1 |
|
|
T1 |
51 |
|
T2 |
9 |
|
T3 |
9 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10717 |
1 |
|
|
T1 |
36 |
|
T2 |
4 |
|
T3 |
4 |
auto[1] |
11155 |
1 |
|
|
T1 |
43 |
|
T2 |
9 |
|
T3 |
6 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1355 |
1 |
|
|
T1 |
6 |
|
T5 |
2 |
|
T8 |
2 |
auto[0] |
auto[0] |
auto[1] |
1185 |
1 |
|
|
T1 |
6 |
|
T3 |
1 |
|
T5 |
3 |
auto[0] |
auto[1] |
auto[0] |
3883 |
1 |
|
|
T1 |
9 |
|
T2 |
1 |
|
T7 |
12 |
auto[0] |
auto[1] |
auto[1] |
3373 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T7 |
15 |
auto[1] |
auto[0] |
auto[0] |
1396 |
1 |
|
|
T1 |
7 |
|
T3 |
3 |
|
T5 |
1 |
auto[1] |
auto[0] |
auto[1] |
1686 |
1 |
|
|
T1 |
9 |
|
T3 |
2 |
|
T8 |
4 |
auto[1] |
auto[1] |
auto[0] |
4083 |
1 |
|
|
T1 |
14 |
|
T2 |
3 |
|
T3 |
1 |
auto[1] |
auto[1] |
auto[1] |
4911 |
1 |
|
|
T1 |
21 |
|
T2 |
6 |
|
T3 |
3 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5622 |
1 |
|
|
T1 |
28 |
|
T3 |
6 |
|
T5 |
6 |
auto[1] |
16250 |
1 |
|
|
T1 |
51 |
|
T2 |
13 |
|
T3 |
4 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9990 |
1 |
|
|
T1 |
37 |
|
T2 |
6 |
|
T3 |
4 |
auto[1] |
11882 |
1 |
|
|
T1 |
42 |
|
T2 |
7 |
|
T3 |
6 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10822 |
1 |
|
|
T1 |
44 |
|
T2 |
7 |
|
T3 |
5 |
auto[1] |
11050 |
1 |
|
|
T1 |
35 |
|
T2 |
6 |
|
T3 |
5 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1377 |
1 |
|
|
T1 |
9 |
|
T3 |
2 |
|
T5 |
1 |
auto[0] |
auto[0] |
auto[1] |
1246 |
1 |
|
|
T1 |
5 |
|
T3 |
1 |
|
T111 |
1 |
auto[0] |
auto[1] |
auto[0] |
3916 |
1 |
|
|
T1 |
15 |
|
T2 |
4 |
|
T7 |
7 |
auto[0] |
auto[1] |
auto[1] |
3451 |
1 |
|
|
T1 |
8 |
|
T2 |
2 |
|
T3 |
1 |
auto[1] |
auto[0] |
auto[0] |
1368 |
1 |
|
|
T1 |
9 |
|
T5 |
2 |
|
T8 |
2 |
auto[1] |
auto[0] |
auto[1] |
1631 |
1 |
|
|
T1 |
5 |
|
T3 |
3 |
|
T5 |
3 |
auto[1] |
auto[1] |
auto[0] |
4161 |
1 |
|
|
T1 |
11 |
|
T2 |
3 |
|
T3 |
3 |
auto[1] |
auto[1] |
auto[1] |
4722 |
1 |
|
|
T1 |
17 |
|
T2 |
4 |
|
T6 |
1 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5622 |
1 |
|
|
T1 |
28 |
|
T3 |
6 |
|
T5 |
6 |
auto[1] |
16250 |
1 |
|
|
T1 |
51 |
|
T2 |
13 |
|
T3 |
4 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9894 |
1 |
|
|
T1 |
37 |
|
T2 |
6 |
|
T3 |
7 |
auto[1] |
11978 |
1 |
|
|
T1 |
42 |
|
T2 |
7 |
|
T3 |
3 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10736 |
1 |
|
|
T1 |
44 |
|
T2 |
6 |
|
T3 |
2 |
auto[1] |
11136 |
1 |
|
|
T1 |
35 |
|
T2 |
7 |
|
T3 |
8 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1417 |
1 |
|
|
T1 |
8 |
|
T3 |
1 |
|
T5 |
2 |
auto[0] |
auto[0] |
auto[1] |
1209 |
1 |
|
|
T1 |
5 |
|
T3 |
4 |
|
T5 |
1 |
auto[0] |
auto[1] |
auto[0] |
3829 |
1 |
|
|
T1 |
12 |
|
T2 |
3 |
|
T7 |
15 |
auto[0] |
auto[1] |
auto[1] |
3439 |
1 |
|
|
T1 |
12 |
|
T2 |
3 |
|
T3 |
2 |
auto[1] |
auto[0] |
auto[0] |
1373 |
1 |
|
|
T1 |
7 |
|
T5 |
2 |
|
T8 |
2 |
auto[1] |
auto[0] |
auto[1] |
1623 |
1 |
|
|
T1 |
8 |
|
T3 |
1 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[0] |
4117 |
1 |
|
|
T1 |
17 |
|
T2 |
3 |
|
T3 |
1 |
auto[1] |
auto[1] |
auto[1] |
4865 |
1 |
|
|
T1 |
10 |
|
T2 |
4 |
|
T3 |
1 |