Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	488273	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

242068

1

T1

995

T2

103

T3

65

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	469845	1			T1	2001		T2	212		T3	107
values[0x0]	130100	1			T1	300		T2	54		T3	49
values[0x1]	130396	1			T1	382		T2	65		T3	56

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	386491	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

343850

1

T1

1353

T2

159

T3

100

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2157	1			T1	10		T2	4		T41	8
valid_sources[0x01]	2163	1			T1	13		T2	4		T3	2
valid_sources[0x02]	2570	1			T1	7		T8	27		T10	2
valid_sources[0x03]	2162	1			T1	9		T5	1		T41	8
valid_sources[0x04]	2716	1			T1	10		T2	1		T3	1
valid_sources[0x05]	3676	1			T1	9		T2	2		T3	1
valid_sources[0x06]	2190	1			T1	6		T2	3		T8	4
valid_sources[0x07]	3655	1			T1	7		T5	1		T10	1
valid_sources[0x08]	5169	1			T1	11		T3	1		T41	1
valid_sources[0x09]	6444	1			T1	9		T2	3		T41	3
valid_sources[0x0a]	3738	1			T1	7		T5	1		T41	1
valid_sources[0x0b]	2333	1			T1	8		T2	3		T3	1
valid_sources[0x0c]	2488	1			T1	9		T2	2		T3	1
valid_sources[0x0d]	1991	1			T1	14		T2	2		T5	1
valid_sources[0x0e]	3698	1			T1	9		T2	1		T3	3
valid_sources[0x0f]	2253	1			T1	17		T2	2		T3	2
valid_sources[0x10]	2249	1			T1	11		T2	2		T3	1
valid_sources[0x11]	2361	1			T1	6		T2	1		T5	2
valid_sources[0x12]	2268	1			T1	12		T8	13		T111	1
valid_sources[0x13]	2148	1			T1	3		T2	1		T5	1
valid_sources[0x14]	2294	1			T1	12		T3	1		T41	11
valid_sources[0x15]	2241	1			T1	12		T2	1		T3	1
valid_sources[0x16]	2217	1			T1	10		T2	2		T3	4
valid_sources[0x17]	2187	1			T1	6		T2	1		T5	1
valid_sources[0x18]	2409	1			T1	4		T3	1		T5	1
valid_sources[0x19]	2203	1			T1	7		T2	1		T5	2
valid_sources[0x1a]	2719	1			T1	15		T3	1		T8	1
valid_sources[0x1b]	2323	1			T1	16		T5	1		T41	5
valid_sources[0x1c]	2254	1			T1	14		T2	2		T3	2
valid_sources[0x1d]	2100	1			T1	9		T3	4		T41	8
valid_sources[0x1e]	2186	1			T1	6		T2	2		T3	1
valid_sources[0x1f]	2217	1			T1	8		T2	1		T3	1
valid_sources[0x20]	2097	1			T1	10		T2	1		T5	1
valid_sources[0x21]	3740	1			T1	3		T3	2		T10	4
valid_sources[0x22]	2263	1			T1	7		T8	7		T41	4
valid_sources[0x23]	2169	1			T1	9		T2	3		T5	1
valid_sources[0x24]	2730	1			T1	4		T5	1		T8	1
valid_sources[0x25]	2041	1			T1	12		T3	1		T10	1
valid_sources[0x26]	6800	1			T1	8		T2	2		T3	2
valid_sources[0x27]	2381	1			T1	11		T2	2		T3	5
valid_sources[0x28]	2139	1			T1	13		T2	1		T3	3
valid_sources[0x29]	2705	1			T1	8		T2	2		T3	4
valid_sources[0x2a]	5598	1			T1	6		T2	1		T5	3
valid_sources[0x2b]	3453	1			T1	14		T3	2		T25	1
valid_sources[0x2c]	1974	1			T1	13		T2	1		T3	2
valid_sources[0x2d]	2051	1			T1	2		T2	2		T3	2
valid_sources[0x2e]	2492	1			T1	9		T2	1		T3	1
valid_sources[0x2f]	2301	1			T1	13		T9	2		T41	5
valid_sources[0x30]	2179	1			T1	2		T2	1		T5	2
valid_sources[0x31]	2181	1			T1	4		T3	2		T41	10
valid_sources[0x32]	2696	1			T1	20		T41	1		T111	1
valid_sources[0x33]	2218	1			T1	13		T2	1		T5	1
valid_sources[0x34]	2030	1			T1	13		T2	4		T3	1
valid_sources[0x35]	2562	1			T1	17		T3	1		T5	2
valid_sources[0x36]	2238	1			T1	23		T29	1		T141	3
valid_sources[0x37]	2222	1			T1	4		T5	2		T9	1
valid_sources[0x38]	2283	1			T1	15		T2	1		T3	2
valid_sources[0x39]	2248	1			T1	13		T2	1		T5	3
valid_sources[0x3a]	2069	1			T1	8		T2	2		T3	2
valid_sources[0x3b]	2712	1			T1	14		T2	4		T5	2
valid_sources[0x3c]	2215	1			T1	6		T2	2		T3	2
valid_sources[0x3d]	2261	1			T1	10		T2	1		T29	1
valid_sources[0x3e]	2161	1			T1	17		T3	1		T5	1
valid_sources[0x3f]	2025	1			T1	12		T5	1		T8	3
valid_sources[0x40]	2268	1			T1	17		T2	2		T3	1
valid_sources[0x41]	7818	1			T1	13		T2	2		T5	1
valid_sources[0x42]	2126	1			T1	8		T5	4		T9	1
valid_sources[0x43]	2133	1			T1	17		T2	1		T41	8
valid_sources[0x44]	2222	1			T1	12		T41	10		T111	1
valid_sources[0x45]	7662	1			T1	7		T2	3		T5	3
valid_sources[0x46]	2097	1			T1	7		T2	1		T5	1
valid_sources[0x47]	2024	1			T1	9		T3	1		T5	5
valid_sources[0x48]	2351	1			T1	11		T2	3		T5	1
valid_sources[0x49]	2116	1			T1	7		T2	3		T41	2
valid_sources[0x4a]	2572	1			T1	16		T2	1		T28	2
valid_sources[0x4b]	2260	1			T1	9		T3	1		T41	4
valid_sources[0x4c]	3309	1			T1	9		T8	13		T41	1
valid_sources[0x4d]	2196	1			T1	9		T8	6		T9	3
valid_sources[0x4e]	2191	1			T1	11		T2	1		T3	1
valid_sources[0x4f]	2144	1			T1	6		T2	1		T3	3
valid_sources[0x50]	1988	1			T1	14		T2	3		T3	1
valid_sources[0x51]	2007	1			T1	3		T41	13		T25	2
valid_sources[0x52]	2897	1			T1	6		T2	5		T3	1
valid_sources[0x53]	2250	1			T1	13		T2	5		T5	2
valid_sources[0x54]	2214	1			T1	7		T2	1		T3	1
valid_sources[0x55]	2174	1			T1	10		T2	2		T8	5
valid_sources[0x56]	2292	1			T1	18		T2	2		T41	1
valid_sources[0x57]	5116	1			T1	5		T2	1		T3	1
valid_sources[0x58]	2172	1			T1	5		T5	2		T41	3
valid_sources[0x59]	2288	1			T1	15		T2	1		T3	2
valid_sources[0x5a]	3883	1			T1	12		T41	8		T29	6
valid_sources[0x5b]	2018	1			T1	9		T3	1		T5	2
valid_sources[0x5c]	2129	1			T1	15		T3	1		T5	1
valid_sources[0x5d]	2218	1			T1	13		T2	1		T3	1
valid_sources[0x5e]	2461	1			T1	12		T41	1		T29	1
valid_sources[0x5f]	2328	1			T1	18		T2	3		T3	2
valid_sources[0x60]	2794	1			T1	11		T2	1		T5	1
valid_sources[0x61]	2254	1			T1	14		T41	10		T29	10
valid_sources[0x62]	2018	1			T1	8		T2	3		T5	1
valid_sources[0x63]	2357	1			T1	19		T9	1		T41	7
valid_sources[0x64]	2238	1			T1	11		T3	1		T5	1
valid_sources[0x65]	2163	1			T1	6		T2	3		T3	1
valid_sources[0x66]	2794	1			T1	13		T8	2		T10	3
valid_sources[0x67]	2123	1			T1	10		T2	1		T5	2
valid_sources[0x68]	2830	1			T1	13		T5	3		T9	1
valid_sources[0x69]	2371	1			T1	7		T5	1		T41	2
valid_sources[0x6a]	1991	1			T1	9		T3	2		T29	3
valid_sources[0x6b]	2352	1			T1	1		T5	1		T41	18
valid_sources[0x6c]	5394	1			T1	5		T2	2		T41	23
valid_sources[0x6d]	2010	1			T1	7		T2	1		T3	1
valid_sources[0x6e]	2186	1			T1	9		T2	1		T69	1
valid_sources[0x6f]	2202	1			T1	13		T2	13		T5	1
valid_sources[0x70]	2769	1			T1	28		T2	1		T41	5
valid_sources[0x71]	2347	1			T1	15		T2	2		T3	1
valid_sources[0x72]	2438	1			T1	14		T3	4		T10	1
valid_sources[0x73]	2159	1			T1	16		T2	1		T3	1
valid_sources[0x74]	2483	1			T1	10		T2	3		T5	1
valid_sources[0x75]	2188	1			T1	17		T41	7		T111	1
valid_sources[0x76]	2347	1			T1	11		T2	1		T5	1
valid_sources[0x77]	2166	1			T1	17		T2	3		T41	5
valid_sources[0x78]	3694	1			T1	7		T2	2		T3	1
valid_sources[0x79]	2319	1			T1	5		T2	2		T3	1
valid_sources[0x7a]	2321	1			T1	9		T2	1		T5	1
valid_sources[0x7b]	2594	1			T1	14		T2	1		T3	2
valid_sources[0x7c]	2132	1			T1	17		T2	1		T5	2
valid_sources[0x7d]	2551	1			T1	9		T3	2		T5	1
valid_sources[0x7e]	2210	1			T1	6		T5	1		T41	4
valid_sources[0x7f]	2093	1			T1	16		T3	1		T5	1
valid_sources[0x80]	3062	1			T1	5		T3	1		T10	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

166391

1

T1

814

T2

71

T3

34

values[0x0]

all_enables

biggest_size

49230

1

T1

112

T2

21

T3

20

values[0x1]

all_enables

biggest_size

26447

1

T1

69

T2

11

T3

11