SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34910 | 1 | T7 | 297 | T24 | 427 | T41 | 378 | ||||
others[1] | 34922 | 1 | T7 | 292 | T24 | 357 | T41 | 419 | ||||
others[2] | 34824 | 1 | T7 | 309 | T24 | 430 | T41 | 424 | ||||
others[3] | 57371 | 1 | T7 | 509 | T24 | 657 | T41 | 652 | ||||
false | 15763 | 1 | T1 | 28 | T2 | 26 | T7 | 50 | ||||
true | 24417 | 1 | T1 | 41 | T2 | 27 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34662 | 1 | T7 | 294 | T24 | 383 | T41 | 406 | ||||
others[1] | 34880 | 1 | T7 | 318 | T24 | 418 | T41 | 383 | ||||
others[2] | 34643 | 1 | T7 | 309 | T24 | 379 | T41 | 386 | ||||
others[3] | 57972 | 1 | T7 | 482 | T24 | 695 | T41 | 694 | ||||
false | 10448 | 1 | T1 | 14 | T2 | 13 | T7 | 50 | ||||
true | 19175 | 1 | T1 | 27 | T2 | 14 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 582 | 1 | T14 | 4 | T133 | 8 | T44 | 1 | ||||
others[1] | 603 | 1 | T14 | 2 | T133 | 5 | T134 | 6 | ||||
others[2] | 589 | 1 | T1 | 2 | T14 | 6 | T133 | 6 | ||||
others[3] | 1013 | 1 | T1 | 2 | T13 | 2 | T28 | 1 | ||||
false | 10963 | 1 | T1 | 28 | T2 | 1 | T3 | 1 | ||||
true | 3142 | 1 | T1 | 11 | T13 | 5 | T28 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |