Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T24,T14

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	20728210	5205	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	20728210	223199	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	20728210	8435866	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	20728210	223189	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	20728210	5205	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	20728210	223199	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	20728210	8435866	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	20728210	223189	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	5205	0	0
T1	47252	10	0	0
T2	5019	2	0	0
T3	5190	0	0	0
T4	15214	0	0	0
T5	6534	0	0	0
T6	2477	1	0	0
T7	59512	18	0	0
T8	4184	0	0	0
T9	2252	0	0	0
T10	4766	0	0	0
T14	0	35	0	0
T24	0	24	0	0
T25	0	1	0	0
T29	0	26	0	0
T41	0	16	0	0
T42	0	15	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	223199	0	0
T1	47252	273	0	0
T2	5019	44	0	0
T3	5190	0	0	0
T4	15214	0	0	0
T5	6534	0	0	0
T6	2477	10	0	0
T7	59512	1275	0	0
T8	4184	0	0	0
T9	2252	0	0	0
T10	4766	0	0	0
T14	0	2286	0	0
T24	0	1422	0	0
T25	0	12	0	0
T29	0	1950	0	0
T41	0	435	0	0
T42	0	210	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	8435866	0	0
T1	47252	23021	0	0
T2	5019	911	0	0
T3	5190	2263	0	0
T4	15214	0	0	0
T5	6534	3494	0	0
T6	2477	1579	0	0
T7	59512	27225	0	0
T8	4184	1705	0	0
T9	2252	1297	0	0
T10	4766	962	0	0
T69	0	1290	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	223189	0	0
T1	47252	273	0	0
T2	5019	44	0	0
T3	5190	0	0	0
T4	15214	0	0	0
T5	6534	0	0	0
T6	2477	10	0	0
T7	59512	1275	0	0
T8	4184	0	0	0
T9	2252	0	0	0
T10	4766	0	0	0
T14	0	2286	0	0
T24	0	1422	0	0
T25	0	12	0	0
T29	0	1952	0	0
T41	0	435	0	0
T42	0	210	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	5205	0	0
T1	47252	10	0	0
T2	5019	2	0	0
T3	5190	0	0	0
T4	15214	0	0	0
T5	6534	0	0	0
T6	2477	1	0	0
T7	59512	18	0	0
T8	4184	0	0	0
T9	2252	0	0	0
T10	4766	0	0	0
T14	0	35	0	0
T24	0	24	0	0
T25	0	1	0	0
T29	0	26	0	0
T41	0	16	0	0
T42	0	15	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	223199	0	0
T1	47252	273	0	0
T2	5019	44	0	0
T3	5190	0	0	0
T4	15214	0	0	0
T5	6534	0	0	0
T6	2477	10	0	0
T7	59512	1275	0	0
T8	4184	0	0	0
T9	2252	0	0	0
T10	4766	0	0	0
T14	0	2286	0	0
T24	0	1422	0	0
T25	0	12	0	0
T29	0	1950	0	0
T41	0	435	0	0
T42	0	210	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	8435866	0	0
T1	47252	23021	0	0
T2	5019	911	0	0
T3	5190	2263	0	0
T4	15214	0	0	0
T5	6534	3494	0	0
T6	2477	1579	0	0
T7	59512	27225	0	0
T8	4184	1705	0	0
T9	2252	1297	0	0
T10	4766	962	0	0
T69	0	1290	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	223189	0	0
T1	47252	273	0	0
T2	5019	44	0	0
T3	5190	0	0	0
T4	15214	0	0	0
T5	6534	0	0	0
T6	2477	10	0	0
T7	59512	1275	0	0
T8	4184	0	0	0
T9	2252	0	0	0
T10	4766	0	0	0
T14	0	2286	0	0
T24	0	1422	0	0
T25	0	12	0	0
T29	0	1952	0	0
T41	0	435	0	0
T42	0	210	0	0