Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	21200858	11972	0	0
intr_enable_rd_A	21200858	19712	0	0
reset_en_rd_A	21200858	1577	0	0
reset_en_regwen_rd_A	21200858	1323	0	0
wake_info_capture_dis_rd_A	21200858	1236	0	0
wakeup_en_rd_A	21200858	2076	0	0
wakeup_en_regwen_rd_A	21200858	1248	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21200858	11972	0	0
T16	75529	2	0	0
T17	999	0	0	0
T26	0	6	0	0
T27	0	262	0	0
T50	1832	0	0	0
T52	1568	0	0	0
T54	0	8	0	0
T55	0	510	0	0
T56	0	9	0	0
T57	0	8	0	0
T58	0	601	0	0
T59	0	667	0	0
T65	0	24	0	0
T105	1916	0	0	0
T106	32075	0	0	0
T107	1314	0	0	0
T108	5825	0	0	0
T109	3596	0	0	0
T110	4461	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21200858	19712	0	0
T3	5190	29	0	0
T4	15214	0	0	0
T5	6534	0	0	0
T6	2477	0	0	0
T7	59512	0	0	0
T8	4184	0	0	0
T9	2252	0	0	0
T10	4766	0	0	0
T13	0	29	0	0
T14	0	610	0	0
T16	0	435	0	0
T24	61607	0	0	0
T29	0	173	0	0
T41	0	114	0	0
T69	1529	0	0	0
T111	0	29	0	0
T112	0	72	0	0
T113	0	64	0	0
T114	0	170	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21200858	1577	0	0
T16	75529	3	0	0
T17	999	0	0	0
T50	1832	0	0	0
T52	1568	0	0	0
T55	0	16	0	0
T56	0	135	0	0
T57	0	138	0	0
T72	0	87	0	0
T82	0	16	0	0
T84	0	70	0	0
T88	0	117	0	0
T91	0	466	0	0
T105	1916	0	0	0
T106	32075	0	0	0
T107	1314	0	0	0
T108	5825	0	0	0
T109	3596	0	0	0
T110	4461	0	0	0
T115	0	2	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21200858	1323	0	0
T16	75529	2	0	0
T17	999	0	0	0
T50	1832	0	0	0
T52	1568	0	0	0
T55	0	17	0	0
T56	0	86	0	0
T57	0	89	0	0
T72	0	42	0	0
T82	0	19	0	0
T84	0	52	0	0
T88	0	131	0	0
T91	0	428	0	0
T105	1916	0	0	0
T106	32075	0	0	0
T107	1314	0	0	0
T108	5825	0	0	0
T109	3596	0	0	0
T110	4461	0	0	0
T115	0	12	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21200858	1236	0	0
T16	75529	7	0	0
T17	999	0	0	0
T50	1832	0	0	0
T52	1568	0	0	0
T55	0	22	0	0
T56	0	86	0	0
T57	0	96	0	0
T72	0	48	0	0
T82	0	20	0	0
T84	0	30	0	0
T88	0	86	0	0
T91	0	420	0	0
T105	1916	0	0	0
T106	32075	0	0	0
T107	1314	0	0	0
T108	5825	0	0	0
T109	3596	0	0	0
T110	4461	0	0	0
T115	0	21	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21200858	2076	0	0
T16	75529	10	0	0
T17	999	0	0	0
T50	1832	0	0	0
T52	1568	0	0	0
T55	0	18	0	0
T56	0	283	0	0
T57	0	298	0	0
T72	0	140	0	0
T82	0	49	0	0
T84	0	47	0	0
T88	0	79	0	0
T91	0	467	0	0
T105	1916	0	0	0
T106	32075	0	0	0
T107	1314	0	0	0
T108	5825	0	0	0
T109	3596	0	0	0
T110	4461	0	0	0
T115	0	19	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21200858	1248	0	0
T16	75529	15	0	0
T17	999	0	0	0
T50	1832	0	0	0
T52	1568	0	0	0
T55	0	20	0	0
T56	0	111	0	0
T57	0	65	0	0
T72	0	30	0	0
T82	0	16	0	0
T84	0	38	0	0
T88	0	87	0	0
T91	0	475	0	0
T105	1916	0	0	0
T106	32075	0	0	0
T107	1314	0	0	0
T108	5825	0	0	0
T109	3596	0	0	0
T110	4461	0	0	0
T115	0	1	0	0