Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	20728210	42793	0	0
IoStatusRise_A	20728210	47606	0	0
MainStatusFall_A	20728210	42793	0	0
MainStatusRise_A	20728210	47606	0	0
UsbStatusFall_A	20728210	32379	0	0
UsbStatusRise_A	20728210	36343	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	42793	0	0
T1	47252	120	0	0
T2	5019	21	0	0
T3	5190	10	0	0
T4	15214	1	0	0
T5	6534	9	0	0
T6	2477	2	0	0
T7	59512	85	0	0
T8	4184	15	0	0
T9	2252	2	0	0
T10	4766	3	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	47606	0	0
T1	47252	133	0	0
T2	5019	22	0	0
T3	5190	11	0	0
T4	15214	2	0	0
T5	6534	10	0	0
T6	2477	3	0	0
T7	59512	86	0	0
T8	4184	16	0	0
T9	2252	3	0	0
T10	4766	4	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	42793	0	0
T1	47252	120	0	0
T2	5019	21	0	0
T3	5190	10	0	0
T4	15214	1	0	0
T5	6534	9	0	0
T6	2477	2	0	0
T7	59512	85	0	0
T8	4184	15	0	0
T9	2252	2	0	0
T10	4766	3	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	47606	0	0
T1	47252	133	0	0
T2	5019	22	0	0
T3	5190	11	0	0
T4	15214	2	0	0
T5	6534	10	0	0
T6	2477	3	0	0
T7	59512	86	0	0
T8	4184	16	0	0
T9	2252	3	0	0
T10	4766	4	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	32379	0	0
T1	47252	94	0	0
T2	5019	13	0	0
T3	5190	9	0	0
T4	15214	1	0	0
T5	6534	8	0	0
T6	2477	2	0	0
T7	59512	44	0	0
T8	4184	12	0	0
T9	2252	2	0	0
T10	4766	1	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	36343	0	0
T1	47252	102	0	0
T2	5019	14	0	0
T3	5190	10	0	0
T4	15214	2	0	0
T5	6534	9	0	0
T6	2477	3	0	0
T7	59512	44	0	0
T8	4184	12	0	0
T9	2252	3	0	0
T10	4766	1	0	0