Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	20728210	47222	0	0
RomAllowCheckGoodState_A	20728210	47272	0	0
RomBlockActiveState_A	20728210	34256	0	0
RomBlockCheckGoodState_A	20728210	381082	0	0
RomIntgChkDisFalse_A	20728210	20189611	0	0
RomIntgChkDisTrue_A	20728210	109976	0	0
RstreqChkEsctimeout_A	20728210	3461	0	0
RstreqChkFsmterm_A	20728210	160	0	0
RstreqChkGlbesc_A	20728210	3462	0	0
RstreqChkMainpd_A	20728210	861646	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	47222	0	0
T1	47252	133	0	0
T2	5019	22	0	0
T3	5190	11	0	0
T4	15214	2	0	0
T5	6534	10	0	0
T6	2477	3	0	0
T7	59512	86	0	0
T8	4184	16	0	0
T9	2252	3	0	0
T10	4766	4	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	47272	0	0
T1	47252	133	0	0
T2	5019	22	0	0
T3	5190	11	0	0
T4	15214	2	0	0
T5	6534	10	0	0
T6	2477	3	0	0
T7	59512	86	0	0
T8	4184	16	0	0
T9	2252	3	0	0
T10	4766	4	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	34256	0	0
T13	6291	0	0	0
T14	162725	0	0	0
T15	2533	0	0	0
T25	3282	0	0	0
T28	5337	931	0	0
T29	62451	0	0	0
T41	24761	4	0	0
T43	3019	589	0	0
T45	0	553	0	0
T111	2931	0	0	0
T116	0	1	0	0
T117	0	450	0	0
T118	0	5	0	0
T119	0	336	0	0
T120	0	1243	0	0
T121	0	17	0	0
T122	9627	0	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	381082	0	0
T1	47252	321	0	0
T2	5019	299	0	0
T3	5190	0	0	0
T4	15214	0	0	0
T5	6534	0	0	0
T6	2477	0	0	0
T7	59512	4134	0	0
T8	4184	0	0	0
T9	2252	0	0	0
T10	4766	0	0	0
T14	0	1606	0	0
T24	0	4001	0	0
T28	0	1066	0	0
T29	0	4122	0	0
T41	0	1288	0	0
T42	0	593	0	0
T43	0	246	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	20189611	0	0
T1	47252	46150	0	0
T2	5019	4961	0	0
T3	5190	5126	0	0
T4	15214	15162	0	0
T5	6534	6450	0	0
T6	2477	2409	0	0
T7	59512	58170	0	0
T8	4184	4126	0	0
T9	2252	2182	0	0
T10	4766	4703	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	109976	0	0
T7	59512	1249	0	0
T8	4184	0	0	0
T9	2252	0	0	0
T10	4766	0	0	0
T13	6291	0	0	0
T24	61607	0	0	0
T25	3282	0	0	0
T28	0	608	0	0
T29	0	2792	0	0
T41	24761	0	0	0
T43	0	103	0	0
T45	0	145	0	0
T69	1529	0	0	0
T111	2931	0	0	0
T116	0	114	0	0
T117	0	95	0	0
T123	0	437	0	0
T124	0	2677	0	0
T125	0	381	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	3461	0	0
T1	47252	7	0	0
T2	5019	0	0	0
T3	5190	0	0	0
T4	15214	1	0	0
T5	6534	0	0	0
T6	2477	0	0	0
T7	59512	0	0	0
T8	4184	0	0	0
T9	2252	0	0	0
T10	4766	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	3	0	0
T14	0	18	0	0
T43	0	2	0	0
T44	0	5	0	0
T45	0	3	0	0
T47	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	160	0	0
T21	13116	20	0	0
T22	0	40	0	0
T23	0	40	0	0
T30	0	40	0	0
T31	0	20	0	0
T32	2221	0	0	0
T33	1806	0	0	0
T34	28660	0	0	0
T35	3586	0	0	0
T36	3072	0	0	0
T37	1737	0	0	0
T38	3053	0	0	0
T39	2099	0	0	0
T40	948	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	3462	0	0
T1	47252	7	0	0
T2	5019	0	0	0
T3	5190	0	0	0
T4	15214	1	0	0
T5	6534	0	0	0
T6	2477	0	0	0
T7	59512	0	0	0
T8	4184	0	0	0
T9	2252	0	0	0
T10	4766	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	3	0	0
T14	0	18	0	0
T43	0	2	0	0
T44	0	5	0	0
T45	0	3	0	0
T47	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20728210	861646	0	0
T1	47252	1370	0	0
T2	5019	118	0	0
T3	5190	0	0	0
T4	15214	0	0	0
T5	6534	0	0	0
T6	2477	0	0	0
T7	59512	6503	0	0
T8	4184	0	0	0
T9	2252	0	0	0
T10	4766	0	0	0
T13	0	728	0	0
T14	0	8820	0	0
T24	0	5032	0	0
T28	0	71	0	0
T29	0	8064	0	0
T41	0	1721	0	0
T42	0	559	0	0