Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4279 |
1 |
|
|
T3 |
13 |
|
T5 |
2 |
|
T7 |
13 |
auto[1] |
13905 |
1 |
|
|
T3 |
6 |
|
T5 |
3 |
|
T7 |
60 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8253 |
1 |
|
|
T3 |
8 |
|
T5 |
1 |
|
T7 |
38 |
auto[1] |
9931 |
1 |
|
|
T3 |
11 |
|
T5 |
4 |
|
T7 |
35 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9071 |
1 |
|
|
T3 |
12 |
|
T5 |
2 |
|
T7 |
31 |
auto[1] |
9113 |
1 |
|
|
T3 |
7 |
|
T5 |
3 |
|
T7 |
42 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1072 |
1 |
|
|
T3 |
6 |
|
T7 |
3 |
|
T9 |
1 |
auto[0] |
auto[0] |
auto[1] |
905 |
1 |
|
|
T7 |
4 |
|
T67 |
3 |
|
T21 |
23 |
auto[0] |
auto[1] |
auto[0] |
3396 |
1 |
|
|
T7 |
14 |
|
T8 |
10 |
|
T9 |
2 |
auto[0] |
auto[1] |
auto[1] |
2880 |
1 |
|
|
T3 |
2 |
|
T5 |
1 |
|
T7 |
17 |
auto[1] |
auto[0] |
auto[0] |
1071 |
1 |
|
|
T3 |
5 |
|
T5 |
1 |
|
T7 |
3 |
auto[1] |
auto[0] |
auto[1] |
1231 |
1 |
|
|
T3 |
2 |
|
T5 |
1 |
|
T7 |
3 |
auto[1] |
auto[1] |
auto[0] |
3532 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T7 |
11 |
auto[1] |
auto[1] |
auto[1] |
4097 |
1 |
|
|
T3 |
3 |
|
T5 |
1 |
|
T7 |
18 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4279 |
1 |
|
|
T3 |
13 |
|
T5 |
2 |
|
T7 |
13 |
auto[1] |
13905 |
1 |
|
|
T3 |
6 |
|
T5 |
3 |
|
T7 |
60 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8143 |
1 |
|
|
T3 |
10 |
|
T5 |
1 |
|
T7 |
36 |
auto[1] |
10041 |
1 |
|
|
T3 |
9 |
|
T5 |
4 |
|
T7 |
37 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8976 |
1 |
|
|
T3 |
15 |
|
T5 |
3 |
|
T7 |
38 |
auto[1] |
9208 |
1 |
|
|
T3 |
4 |
|
T5 |
2 |
|
T7 |
35 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1023 |
1 |
|
|
T3 |
5 |
|
T7 |
3 |
|
T9 |
1 |
auto[0] |
auto[0] |
auto[1] |
911 |
1 |
|
|
T3 |
2 |
|
T7 |
5 |
|
T9 |
1 |
auto[0] |
auto[1] |
auto[0] |
3273 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T7 |
12 |
auto[0] |
auto[1] |
auto[1] |
2936 |
1 |
|
|
T3 |
2 |
|
T7 |
16 |
|
T8 |
13 |
auto[1] |
auto[0] |
auto[0] |
1086 |
1 |
|
|
T3 |
6 |
|
T5 |
1 |
|
T7 |
4 |
auto[1] |
auto[0] |
auto[1] |
1259 |
1 |
|
|
T5 |
1 |
|
T7 |
1 |
|
T67 |
4 |
auto[1] |
auto[1] |
auto[0] |
3594 |
1 |
|
|
T3 |
3 |
|
T5 |
1 |
|
T7 |
19 |
auto[1] |
auto[1] |
auto[1] |
4102 |
1 |
|
|
T5 |
1 |
|
T7 |
13 |
|
T8 |
9 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4279 |
1 |
|
|
T3 |
13 |
|
T5 |
2 |
|
T7 |
13 |
auto[1] |
13905 |
1 |
|
|
T3 |
6 |
|
T5 |
3 |
|
T7 |
60 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8126 |
1 |
|
|
T3 |
12 |
|
T5 |
4 |
|
T7 |
34 |
auto[1] |
10058 |
1 |
|
|
T3 |
7 |
|
T5 |
1 |
|
T7 |
39 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9116 |
1 |
|
|
T3 |
13 |
|
T5 |
2 |
|
T7 |
47 |
auto[1] |
9068 |
1 |
|
|
T3 |
6 |
|
T5 |
3 |
|
T7 |
26 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1075 |
1 |
|
|
T3 |
6 |
|
T5 |
1 |
|
T7 |
5 |
auto[0] |
auto[0] |
auto[1] |
911 |
1 |
|
|
T3 |
2 |
|
T7 |
1 |
|
T67 |
1 |
auto[0] |
auto[1] |
auto[0] |
3344 |
1 |
|
|
T3 |
3 |
|
T5 |
1 |
|
T7 |
17 |
auto[0] |
auto[1] |
auto[1] |
2796 |
1 |
|
|
T3 |
1 |
|
T5 |
2 |
|
T7 |
11 |
auto[1] |
auto[0] |
auto[0] |
1066 |
1 |
|
|
T3 |
3 |
|
T7 |
5 |
|
T67 |
4 |
auto[1] |
auto[0] |
auto[1] |
1227 |
1 |
|
|
T3 |
2 |
|
T5 |
1 |
|
T7 |
2 |
auto[1] |
auto[1] |
auto[0] |
3631 |
1 |
|
|
T3 |
1 |
|
T7 |
20 |
|
T8 |
11 |
auto[1] |
auto[1] |
auto[1] |
4134 |
1 |
|
|
T3 |
1 |
|
T7 |
12 |
|
T8 |
14 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4279 |
1 |
|
|
T3 |
13 |
|
T5 |
2 |
|
T7 |
13 |
auto[1] |
13905 |
1 |
|
|
T3 |
6 |
|
T5 |
3 |
|
T7 |
60 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8104 |
1 |
|
|
T3 |
10 |
|
T5 |
1 |
|
T7 |
35 |
auto[1] |
10080 |
1 |
|
|
T3 |
9 |
|
T5 |
4 |
|
T7 |
38 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8821 |
1 |
|
|
T3 |
11 |
|
T5 |
3 |
|
T7 |
30 |
auto[1] |
9363 |
1 |
|
|
T3 |
8 |
|
T5 |
2 |
|
T7 |
43 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
987 |
1 |
|
|
T3 |
4 |
|
T7 |
3 |
|
T9 |
1 |
auto[0] |
auto[0] |
auto[1] |
942 |
1 |
|
|
T3 |
4 |
|
T7 |
2 |
|
T9 |
1 |
auto[0] |
auto[1] |
auto[0] |
3267 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T7 |
12 |
auto[0] |
auto[1] |
auto[1] |
2908 |
1 |
|
|
T3 |
1 |
|
T7 |
18 |
|
T8 |
7 |
auto[1] |
auto[0] |
auto[0] |
1045 |
1 |
|
|
T3 |
5 |
|
T5 |
1 |
|
T7 |
2 |
auto[1] |
auto[0] |
auto[1] |
1305 |
1 |
|
|
T5 |
1 |
|
T7 |
6 |
|
T67 |
3 |
auto[1] |
auto[1] |
auto[0] |
3522 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T7 |
13 |
auto[1] |
auto[1] |
auto[1] |
4208 |
1 |
|
|
T3 |
3 |
|
T5 |
1 |
|
T7 |
17 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4279 |
1 |
|
|
T3 |
13 |
|
T5 |
2 |
|
T7 |
13 |
auto[1] |
13905 |
1 |
|
|
T3 |
6 |
|
T5 |
3 |
|
T7 |
60 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8200 |
1 |
|
|
T3 |
7 |
|
T5 |
3 |
|
T7 |
33 |
auto[1] |
9984 |
1 |
|
|
T3 |
12 |
|
T5 |
2 |
|
T7 |
40 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8837 |
1 |
|
|
T3 |
6 |
|
T5 |
3 |
|
T7 |
30 |
auto[1] |
9347 |
1 |
|
|
T3 |
13 |
|
T5 |
2 |
|
T7 |
43 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1061 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T7 |
2 |
auto[0] |
auto[0] |
auto[1] |
924 |
1 |
|
|
T3 |
5 |
|
T7 |
2 |
|
T9 |
1 |
auto[0] |
auto[1] |
auto[0] |
3271 |
1 |
|
|
T5 |
1 |
|
T7 |
13 |
|
T8 |
6 |
auto[0] |
auto[1] |
auto[1] |
2944 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T7 |
16 |
auto[1] |
auto[0] |
auto[0] |
1001 |
1 |
|
|
T3 |
3 |
|
T5 |
1 |
|
T7 |
2 |
auto[1] |
auto[0] |
auto[1] |
1293 |
1 |
|
|
T3 |
4 |
|
T7 |
7 |
|
T67 |
3 |
auto[1] |
auto[1] |
auto[0] |
3504 |
1 |
|
|
T3 |
2 |
|
T7 |
13 |
|
T8 |
22 |
auto[1] |
auto[1] |
auto[1] |
4186 |
1 |
|
|
T3 |
3 |
|
T5 |
1 |
|
T7 |
18 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4279 |
1 |
|
|
T3 |
13 |
|
T5 |
2 |
|
T7 |
13 |
auto[1] |
13905 |
1 |
|
|
T3 |
6 |
|
T5 |
3 |
|
T7 |
60 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8206 |
1 |
|
|
T3 |
4 |
|
T5 |
1 |
|
T7 |
34 |
auto[1] |
9978 |
1 |
|
|
T3 |
15 |
|
T5 |
4 |
|
T7 |
39 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9012 |
1 |
|
|
T3 |
8 |
|
T5 |
1 |
|
T7 |
36 |
auto[1] |
9172 |
1 |
|
|
T3 |
11 |
|
T5 |
4 |
|
T7 |
37 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1049 |
1 |
|
|
T3 |
2 |
|
T7 |
1 |
|
T67 |
3 |
auto[0] |
auto[0] |
auto[1] |
924 |
1 |
|
|
T5 |
1 |
|
T7 |
4 |
|
T67 |
3 |
auto[0] |
auto[1] |
auto[0] |
3366 |
1 |
|
|
T3 |
2 |
|
T7 |
15 |
|
T8 |
11 |
auto[0] |
auto[1] |
auto[1] |
2867 |
1 |
|
|
T7 |
14 |
|
T8 |
9 |
|
T28 |
5 |
auto[1] |
auto[0] |
auto[0] |
1075 |
1 |
|
|
T3 |
1 |
|
T7 |
4 |
|
T9 |
1 |
auto[1] |
auto[0] |
auto[1] |
1231 |
1 |
|
|
T3 |
10 |
|
T5 |
1 |
|
T7 |
4 |
auto[1] |
auto[1] |
auto[0] |
3522 |
1 |
|
|
T3 |
3 |
|
T5 |
1 |
|
T7 |
16 |
auto[1] |
auto[1] |
auto[1] |
4150 |
1 |
|
|
T3 |
1 |
|
T5 |
2 |
|
T7 |
15 |