Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	420848	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

216471

1

T1

33

T3

181

T4

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	410478	1			T1	76		T2	21		T3	310
values[0x0]	112875	1			T1	10		T3	100		T4	15
values[0x1]	113966	1			T1	12		T3	100		T4	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	333410	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

303909

1

T1

50

T2

9

T3

238

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2070	1			T1	1		T5	1		T8	3
valid_sources[0x01]	1933	1			T3	1		T8	2		T28	1
valid_sources[0x02]	1970	1			T3	4		T8	1		T9	2
valid_sources[0x03]	2275	1			T1	2		T3	2		T8	2
valid_sources[0x04]	2126	1			T1	1		T3	3		T8	3
valid_sources[0x05]	1934	1			T3	1		T5	1		T52	1
valid_sources[0x06]	2058	1			T1	1		T8	9		T28	1
valid_sources[0x07]	2131	1			T3	1		T8	8		T28	2
valid_sources[0x08]	1803	1			T3	4		T8	8		T52	1
valid_sources[0x09]	2086	1			T1	1		T3	1		T8	6
valid_sources[0x0a]	1914	1			T3	2		T8	3		T9	1
valid_sources[0x0b]	1979	1			T8	8		T9	1		T28	2
valid_sources[0x0c]	2432	1			T3	2		T8	10		T52	1
valid_sources[0x0d]	1997	1			T3	2		T8	3		T67	2
valid_sources[0x0e]	2112	1			T3	2		T8	1		T9	1
valid_sources[0x0f]	1856	1			T1	1		T3	3		T52	1
valid_sources[0x10]	2078	1			T3	1		T8	3		T28	4
valid_sources[0x11]	1887	1			T3	4		T8	19		T28	4
valid_sources[0x12]	2526	1			T9	1		T28	1		T29	1
valid_sources[0x13]	1828	1			T1	1		T3	3		T4	15
valid_sources[0x14]	1921	1			T3	1		T8	9		T13	1
valid_sources[0x15]	2196	1			T3	4		T28	1		T67	3
valid_sources[0x16]	2193	1			T3	3		T5	1		T8	6
valid_sources[0x17]	2607	1			T3	2		T8	2		T13	1
valid_sources[0x18]	1863	1			T13	3		T67	1		T24	2
valid_sources[0x19]	1906	1			T8	4		T9	2		T52	1
valid_sources[0x1a]	2343	1			T3	1		T28	1		T67	2
valid_sources[0x1b]	1795	1			T3	3		T4	3		T6	1
valid_sources[0x1c]	2152	1			T1	1		T3	2		T8	5
valid_sources[0x1d]	2092	1			T8	5		T9	2		T10	1
valid_sources[0x1e]	2209	1			T1	1		T3	2		T8	2
valid_sources[0x1f]	2153	1			T28	1		T67	2		T30	3
valid_sources[0x20]	1897	1			T3	5		T5	1		T13	1
valid_sources[0x21]	2268	1			T3	1		T8	8		T10	3
valid_sources[0x22]	3145	1			T1	3		T3	3		T8	3
valid_sources[0x23]	2014	1			T1	1		T3	3		T4	3
valid_sources[0x24]	2717	1			T3	2		T8	5		T28	1
valid_sources[0x25]	3792	1			T3	4		T5	1		T28	1
valid_sources[0x26]	2028	1			T8	1		T52	1		T28	1
valid_sources[0x27]	1890	1			T3	1		T8	2		T9	2
valid_sources[0x28]	2115	1			T1	2		T3	4		T4	12
valid_sources[0x29]	1964	1			T3	3		T8	3		T67	2
valid_sources[0x2a]	1909	1			T3	2		T8	5		T52	2
valid_sources[0x2b]	2048	1			T3	2		T4	1		T10	1
valid_sources[0x2c]	2217	1			T1	1		T8	9		T9	1
valid_sources[0x2d]	2167	1			T1	2		T3	4		T8	4
valid_sources[0x2e]	2182	1			T1	2		T8	6		T9	1
valid_sources[0x2f]	2026	1			T3	3		T5	1		T8	17
valid_sources[0x30]	2133	1			T4	1		T8	6		T67	2
valid_sources[0x31]	2227	1			T3	2		T8	4		T52	1
valid_sources[0x32]	1822	1			T3	4		T8	2		T20	1
valid_sources[0x33]	1915	1			T3	7		T4	3		T9	1
valid_sources[0x34]	2177	1			T3	5		T8	5		T13	1
valid_sources[0x35]	2154	1			T3	1		T8	4		T67	1
valid_sources[0x36]	2118	1			T8	3		T52	1		T14	4
valid_sources[0x37]	1759	1			T3	3		T28	2		T67	2
valid_sources[0x38]	1955	1			T1	1		T3	1		T9	2
valid_sources[0x39]	2202	1			T3	2		T5	1		T52	1
valid_sources[0x3a]	6407	1			T4	5		T8	6		T9	1
valid_sources[0x3b]	3388	1			T3	4		T8	1		T13	2
valid_sources[0x3c]	2016	1			T1	1		T3	3		T8	3
valid_sources[0x3d]	5999	1			T1	2		T3	2		T8	1
valid_sources[0x3e]	2192	1			T3	1		T5	1		T8	4
valid_sources[0x3f]	2019	1			T3	2		T9	1		T52	1
valid_sources[0x40]	2366	1			T3	2		T5	4		T8	3
valid_sources[0x41]	8268	1			T1	1		T3	3		T28	4
valid_sources[0x42]	1721	1			T3	1		T8	6		T28	3
valid_sources[0x43]	2145	1			T3	1		T8	1		T9	2
valid_sources[0x44]	2189	1			T3	2		T5	1		T8	17
valid_sources[0x45]	2001	1			T3	1		T9	1		T14	2
valid_sources[0x46]	2037	1			T3	2		T8	10		T67	1
valid_sources[0x47]	3851	1			T3	2		T8	3		T13	1
valid_sources[0x48]	1996	1			T3	1		T9	1		T28	3
valid_sources[0x49]	2089	1			T3	1		T5	4		T8	5
valid_sources[0x4a]	2466	1			T1	1		T3	2		T8	1
valid_sources[0x4b]	3703	1			T3	1		T52	1		T13	1
valid_sources[0x4c]	2115	1			T8	13		T28	1		T67	1
valid_sources[0x4d]	1971	1			T3	1		T8	1		T10	5
valid_sources[0x4e]	3189	1			T3	1		T5	1		T8	12
valid_sources[0x4f]	3270	1			T1	1		T3	1		T4	11
valid_sources[0x50]	2009	1			T8	1		T9	1		T28	3
valid_sources[0x51]	4175	1			T3	5		T8	9		T9	1
valid_sources[0x52]	1994	1			T8	2		T28	2		T67	2
valid_sources[0x53]	2258	1			T3	3		T28	2		T67	1
valid_sources[0x54]	2016	1			T3	1		T8	1		T67	3
valid_sources[0x55]	1957	1			T1	4		T3	2		T8	4
valid_sources[0x56]	1794	1			T3	4		T8	4		T28	4
valid_sources[0x57]	2162	1			T3	1		T8	6		T9	1
valid_sources[0x58]	3205	1			T3	1		T9	2		T28	2
valid_sources[0x59]	2240	1			T1	1		T3	3		T8	2
valid_sources[0x5a]	1980	1			T1	1		T3	2		T8	8
valid_sources[0x5b]	1923	1			T1	1		T3	2		T28	3
valid_sources[0x5c]	1933	1			T3	3		T5	1		T8	3
valid_sources[0x5d]	1928	1			T3	2		T8	10		T9	2
valid_sources[0x5e]	3189	1			T1	1		T3	4		T8	12
valid_sources[0x5f]	8315	1			T3	7		T9	1		T52	1
valid_sources[0x60]	1958	1			T3	4		T9	1		T52	1
valid_sources[0x61]	2605	1			T3	5		T8	1		T52	2
valid_sources[0x62]	1974	1			T1	1		T3	4		T8	6
valid_sources[0x63]	1842	1			T3	6		T8	6		T28	1
valid_sources[0x64]	1943	1			T3	1		T5	17		T8	4
valid_sources[0x65]	3665	1			T1	1		T3	1		T8	5
valid_sources[0x66]	1878	1			T3	2		T8	5		T28	1
valid_sources[0x67]	1909	1			T3	4		T8	1		T13	2
valid_sources[0x68]	2013	1			T1	2		T3	1		T8	6
valid_sources[0x69]	2044	1			T3	5		T52	1		T14	16
valid_sources[0x6a]	1957	1			T1	1		T3	1		T9	1
valid_sources[0x6b]	4167	1			T1	1		T8	2		T9	1
valid_sources[0x6c]	1851	1			T8	14		T28	2		T67	4
valid_sources[0x6d]	3284	1			T1	1		T3	2		T8	1
valid_sources[0x6e]	2268	1			T1	1		T3	2		T8	2
valid_sources[0x6f]	3776	1			T10	3		T52	1		T14	10
valid_sources[0x70]	2016	1			T1	1		T3	5		T8	14
valid_sources[0x71]	3227	1			T8	11		T9	2		T28	1
valid_sources[0x72]	2032	1			T1	1		T3	3		T8	21
valid_sources[0x73]	2074	1			T3	5		T8	10		T28	2
valid_sources[0x74]	2424	1			T1	2		T3	1		T8	20
valid_sources[0x75]	5161	1			T3	1		T8	3		T9	2
valid_sources[0x76]	2374	1			T3	1		T5	1		T8	7
valid_sources[0x77]	1915	1			T3	5		T8	16		T9	1
valid_sources[0x78]	2028	1			T3	1		T28	1		T29	2
valid_sources[0x79]	2250	1			T9	1		T52	1		T13	1
valid_sources[0x7a]	6182	1			T1	2		T3	4		T8	4
valid_sources[0x7b]	2043	1			T3	2		T5	2		T13	3
valid_sources[0x7c]	1970	1			T1	2		T3	4		T8	6
valid_sources[0x7d]	2870	1			T1	1		T3	4		T8	3
valid_sources[0x7e]	2393	1			T3	3		T5	2		T8	3
valid_sources[0x7f]	3803	1			T8	5		T67	2		T29	1
valid_sources[0x80]	2423	1			T3	4		T24	1		T30	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

148313

1

T1

27

T3

131

T4

16

values[0x0]

all_enables

biggest_size

43571

1

T1

4

T3

34

T4

4

values[0x1]

all_enables

biggest_size

24587

1

T1

2

T3

16

T4

4