SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34880 | 1 | T8 | 403 | T24 | 292 | T30 | 331 | ||||
others[1] | 35187 | 1 | T8 | 414 | T24 | 308 | T30 | 293 | ||||
others[2] | 35188 | 1 | T8 | 397 | T24 | 301 | T30 | 287 | ||||
others[3] | 58351 | 1 | T8 | 656 | T24 | 494 | T30 | 481 | ||||
false | 13320 | 1 | T1 | 1 | T7 | 78 | T8 | 50 | ||||
true | 21344 | 1 | T1 | 2 | T2 | 81 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35224 | 1 | T8 | 423 | T24 | 287 | T30 | 304 | ||||
others[1] | 35071 | 1 | T8 | 401 | T24 | 292 | T30 | 295 | ||||
others[2] | 34626 | 1 | T8 | 393 | T24 | 319 | T30 | 304 | ||||
others[3] | 58453 | 1 | T8 | 648 | T24 | 494 | T30 | 503 | ||||
false | 9260 | 1 | T1 | 3 | T7 | 39 | T8 | 50 | ||||
true | 17328 | 1 | T1 | 4 | T2 | 81 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 526 | 1 | T122 | 6 | T21 | 13 | T118 | 6 | ||||
others[1] | 505 | 1 | T29 | 1 | T122 | 6 | T21 | 10 | ||||
others[2] | 506 | 1 | T4 | 2 | T7 | 1 | T29 | 2 | ||||
others[3] | 858 | 1 | T4 | 1 | T7 | 1 | T29 | 1 | ||||
false | 9264 | 1 | T1 | 5 | T2 | 81 | T3 | 1 | ||||
true | 2461 | 1 | T1 | 4 | T4 | 5 | T7 | 13 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |