Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T28

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	16790386	4648	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	16790386	200921	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	16790386	6849279	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	16790386	200888	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	16790386	4648	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	16790386	200921	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	16790386	6849279	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	16790386	200888	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	4648	0	0
T7	104514	20	0	0
T8	64301	27	0	0
T9	9427	0	0	0
T10	2848	0	0	0
T13	1646	0	0	0
T14	1828	0	0	0
T20	1237	1	0	0
T24	0	27	0	0
T27	899	0	0	0
T28	17674	10	0	0
T30	0	24	0	0
T31	0	7	0	0
T35	0	3	0	0
T52	2926	1	0	0
T66	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	200921	0	0
T7	104514	952	0	0
T8	64301	1593	0	0
T9	9427	0	0	0
T10	2848	0	0	0
T13	1646	0	0	0
T14	1828	0	0	0
T20	1237	10	0	0
T24	0	706	0	0
T27	899	0	0	0
T28	17674	575	0	0
T30	0	550	0	0
T31	0	137	0	0
T35	0	725	0	0
T52	2926	10	0	0
T66	0	9	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	6849279	0	0
T3	6269	2826	0	0
T4	4768	0	0	0
T5	1912	1461	0	0
T6	2444	0	0	0
T7	104514	41477	0	0
T8	64301	38342	0	0
T9	9427	2946	0	0
T10	2848	0	0	0
T13	0	745	0	0
T14	0	717	0	0
T20	1237	915	0	0
T27	899	0	0	0
T28	0	12021	0	0
T52	0	1760	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	200888	0	0
T7	104514	952	0	0
T8	64301	1593	0	0
T9	9427	0	0	0
T10	2848	0	0	0
T13	1646	0	0	0
T14	1828	0	0	0
T20	1237	10	0	0
T24	0	708	0	0
T27	899	0	0	0
T28	17674	577	0	0
T30	0	550	0	0
T31	0	137	0	0
T35	0	725	0	0
T52	2926	10	0	0
T66	0	9	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	4648	0	0
T7	104514	20	0	0
T8	64301	27	0	0
T9	9427	0	0	0
T10	2848	0	0	0
T13	1646	0	0	0
T14	1828	0	0	0
T20	1237	1	0	0
T24	0	27	0	0
T27	899	0	0	0
T28	17674	10	0	0
T30	0	24	0	0
T31	0	7	0	0
T35	0	3	0	0
T52	2926	1	0	0
T66	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	200921	0	0
T7	104514	952	0	0
T8	64301	1593	0	0
T9	9427	0	0	0
T10	2848	0	0	0
T13	1646	0	0	0
T14	1828	0	0	0
T20	1237	10	0	0
T24	0	706	0	0
T27	899	0	0	0
T28	17674	575	0	0
T30	0	550	0	0
T31	0	137	0	0
T35	0	725	0	0
T52	2926	10	0	0
T66	0	9	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	6849279	0	0
T3	6269	2826	0	0
T4	4768	0	0	0
T5	1912	1461	0	0
T6	2444	0	0	0
T7	104514	41477	0	0
T8	64301	38342	0	0
T9	9427	2946	0	0
T10	2848	0	0	0
T13	0	745	0	0
T14	0	717	0	0
T20	1237	915	0	0
T27	899	0	0	0
T28	0	12021	0	0
T52	0	1760	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	200888	0	0
T7	104514	952	0	0
T8	64301	1593	0	0
T9	9427	0	0	0
T10	2848	0	0	0
T13	1646	0	0	0
T14	1828	0	0	0
T20	1237	10	0	0
T24	0	708	0	0
T27	899	0	0	0
T28	17674	577	0	0
T30	0	550	0	0
T31	0	137	0	0
T35	0	725	0	0
T52	2926	10	0	0
T66	0	9	0	0