Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	17367018	15344	0	0
intr_enable_rd_A	17367018	13771	0	0
reset_en_rd_A	17367018	1022	0	0
reset_en_regwen_rd_A	17367018	904	0	0
wake_info_capture_dis_rd_A	17367018	765	0	0
wakeup_en_rd_A	17367018	1756	0	0
wakeup_en_regwen_rd_A	17367018	813	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17367018	15344	0	0
T16	2709	0	0	0
T21	419823	35	0	0
T22	0	12	0	0
T23	0	7	0	0
T32	5530	0	0	0
T33	3307	0	0	0
T40	0	732	0	0
T41	0	7	0	0
T42	0	11	0	0
T43	0	134	0	0
T44	0	10	0	0
T45	0	321	0	0
T46	0	283	0	0
T47	15004	0	0	0
T117	19836	0	0	0
T118	4885	0	0	0
T119	2980	0	0	0
T120	10792	0	0	0
T121	4212	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17367018	13771	0	0
T7	104514	417	0	0
T8	64301	156	0	0
T9	9427	19	0	0
T10	2848	7	0	0
T13	1646	0	0	0
T14	1828	0	0	0
T20	1237	10	0	0
T24	0	108	0	0
T27	899	0	0	0
T28	17674	22	0	0
T31	0	47	0	0
T52	2926	0	0	0
T67	0	49	0	0
T122	0	127	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17367018	1022	0	0
T40	9196	1	0	0
T42	11306	104	0	0
T44	7261	0	0	0
T45	4423	0	0	0
T54	0	22	0	0
T61	0	22	0	0
T63	0	4	0	0
T86	1219	0	0	0
T87	1427	0	0	0
T88	1754	0	0	0
T89	2317	0	0	0
T90	1214	0	0	0
T95	0	4	0	0
T105	0	53	0	0
T123	14121	128	0	0
T124	0	10	0	0
T125	0	4	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17367018	904	0	0
T40	9196	23	0	0
T42	11306	74	0	0
T44	7261	0	0	0
T45	4423	0	0	0
T54	0	11	0	0
T61	0	17	0	0
T86	1219	0	0	0
T87	1427	0	0	0
T88	1754	0	0	0
T89	2317	0	0	0
T90	1214	0	0	0
T95	0	8	0	0
T105	0	52	0	0
T123	14121	158	0	0
T124	0	1	0	0
T125	0	24	0	0
T126	0	16	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17367018	765	0	0
T40	9196	11	0	0
T42	11306	60	0	0
T44	7261	0	0	0
T45	4423	0	0	0
T54	0	29	0	0
T61	0	11	0	0
T63	0	8	0	0
T86	1219	0	0	0
T87	1427	0	0	0
T88	1754	0	0	0
T89	2317	0	0	0
T90	1214	0	0	0
T95	0	1	0	0
T105	0	70	0	0
T123	14121	108	0	0
T124	0	7	0	0
T125	0	12	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17367018	1756	0	0
T40	9196	3	0	0
T42	11306	307	0	0
T44	7261	0	0	0
T45	4423	0	0	0
T54	0	63	0	0
T61	0	22	0	0
T63	0	10	0	0
T86	1219	0	0	0
T87	1427	0	0	0
T88	1754	0	0	0
T89	2317	0	0	0
T90	1214	0	0	0
T95	0	7	0	0
T105	0	67	0	0
T123	14121	94	0	0
T124	0	3	0	0
T125	0	24	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17367018	813	0	0
T40	9196	20	0	0
T42	11306	87	0	0
T44	7261	0	0	0
T45	4423	0	0	0
T54	0	19	0	0
T61	0	28	0	0
T63	0	9	0	0
T86	1219	0	0	0
T87	1427	0	0	0
T88	1754	0	0	0
T89	2317	0	0	0
T90	1214	0	0	0
T95	0	7	0	0
T105	0	51	0	0
T123	14121	113	0	0
T124	0	16	0	0
T125	0	3	0	0