Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	16790386	39304	0	0
RomAllowCheckGoodState_A	16790386	39353	0	0
RomBlockActiveState_A	16790386	28621	0	0
RomBlockCheckGoodState_A	16790386	359826	0	0
RomIntgChkDisFalse_A	16790386	16285715	0	0
RomIntgChkDisTrue_A	16790386	132137	0	0
RstreqChkEsctimeout_A	16790386	2684	0	0
RstreqChkFsmterm_A	16790386	160	0	0
RstreqChkGlbesc_A	16790386	2687	0	0
RstreqChkMainpd_A	16790386	730019	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	39304	0	0
T1	1609	6	0	0
T2	23199	101	0	0
T3	6269	20	0	0
T4	4768	12	0	0
T5	1912	6	0	0
T6	2444	3	0	0
T7	104514	176	0	0
T8	64301	93	0	0
T9	9427	9	0	0
T10	2848	6	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	39353	0	0
T1	1609	6	0	0
T2	23199	101	0	0
T3	6269	20	0	0
T4	4768	13	0	0
T5	1912	6	0	0
T6	2444	3	0	0
T7	104514	176	0	0
T8	64301	93	0	0
T9	9427	9	0	0
T10	2848	6	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	28621	0	0
T1	1609	180	0	0
T2	23199	0	0	0
T3	6269	0	0	0
T4	4768	0	0	0
T5	1912	0	0	0
T6	2444	0	0	0
T7	104514	0	0	0
T8	64301	0	0	0
T9	9427	0	0	0
T10	2848	553	0	0
T24	0	1	0	0
T30	0	19	0	0
T32	0	1222	0	0
T33	0	526	0	0
T81	0	5	0	0
T84	0	516	0	0
T127	0	7	0	0
T128	0	3	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	359826	0	0
T1	1609	54	0	0
T2	23199	0	0	0
T3	6269	0	0	0
T4	4768	0	0	0
T5	1912	0	0	0
T6	2444	0	0	0
T7	104514	895	0	0
T8	64301	4012	0	0
T9	9427	0	0	0
T10	2848	282	0	0
T21	0	1628	0	0
T24	0	1288	0	0
T28	0	345	0	0
T30	0	1283	0	0
T31	0	458	0	0
T117	0	389	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	16285715	0	0
T1	1609	1439	0	0
T2	23199	16826	0	0
T3	6269	6190	0	0
T4	4768	3839	0	0
T5	1912	1814	0	0
T6	2444	2271	0	0
T7	104514	102779	0	0
T8	64301	64143	0	0
T9	9427	9296	0	0
T10	2848	2676	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	132137	0	0
T1	1609	70	0	0
T2	23199	0	0	0
T3	6269	0	0	0
T4	4768	0	0	0
T5	1912	0	0	0
T6	2444	0	0	0
T7	104514	0	0	0
T8	64301	0	0	0
T9	9427	0	0	0
T10	2848	111	0	0
T24	0	267	0	0
T30	0	292	0	0
T32	0	590	0	0
T33	0	1169	0	0
T78	0	874	0	0
T81	0	61	0	0
T127	0	368	0	0
T129	0	1693	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	2684	0	0
T1	1609	2	0	0
T2	23199	20	0	0
T3	6269	0	0	0
T4	4768	7	0	0
T5	1912	0	0	0
T6	2444	1	0	0
T7	104514	9	0	0
T8	64301	0	0	0
T9	9427	0	0	0
T10	2848	5	0	0
T11	0	1	0	0
T21	0	81	0	0
T29	0	9	0	0
T32	0	3	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	160	0	0
T2	23199	40	0	0
T3	6269	0	0	0
T4	4768	0	0	0
T5	1912	0	0	0
T6	2444	0	0	0
T7	104514	0	0	0
T8	64301	0	0	0
T9	9427	0	0	0
T10	2848	0	0	0
T18	0	40	0	0
T19	0	20	0	0
T25	0	40	0	0
T26	0	20	0	0
T27	899	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	2687	0	0
T1	1609	2	0	0
T2	23199	20	0	0
T3	6269	0	0	0
T4	4768	7	0	0
T5	1912	0	0	0
T6	2444	1	0	0
T7	104514	9	0	0
T8	64301	0	0	0
T9	9427	0	0	0
T10	2848	5	0	0
T11	0	1	0	0
T21	0	81	0	0
T29	0	9	0	0
T32	0	3	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16790386	730019	0	0
T1	1609	54	0	0
T2	23199	0	0	0
T3	6269	0	0	0
T4	4768	152	0	0
T5	1912	0	0	0
T6	2444	0	0	0
T7	104514	3905	0	0
T8	64301	5761	0	0
T9	9427	0	0	0
T10	2848	0	0	0
T24	0	2344	0	0
T27	0	10	0	0
T28	0	1222	0	0
T29	0	329	0	0
T30	0	1917	0	0
T31	0	333	0	0