Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	440286	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

223978

1

T1

100

T2

14

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	427437	1			T1	189		T2	10		T3	22
values[0x0]	118296	1			T1	38		T2	9		T3	5
values[0x1]	118531	1			T1	32		T2	7		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	349077	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

315187

1

T1

137

T2

14

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2022	1			T5	1		T10	5		T14	25
valid_sources[0x01]	2023	1			T8	2		T10	2		T42	2
valid_sources[0x02]	1866	1			T8	2		T10	3		T14	20
valid_sources[0x03]	3639	1			T8	3		T10	2		T14	44
valid_sources[0x04]	2078	1			T8	1		T10	4		T42	2
valid_sources[0x05]	2216	1			T10	2		T42	6		T14	45
valid_sources[0x06]	2587	1			T10	9		T42	1		T14	33
valid_sources[0x07]	2075	1			T8	1		T10	1		T42	1
valid_sources[0x08]	2203	1			T10	1		T14	28		T39	27
valid_sources[0x09]	2182	1			T2	1		T5	3		T8	2
valid_sources[0x0a]	2036	1			T8	2		T10	5		T14	56
valid_sources[0x0b]	2074	1			T7	14		T8	4		T10	6
valid_sources[0x0c]	1961	1			T7	2		T8	1		T10	5
valid_sources[0x0d]	2210	1			T4	2		T5	1		T8	3
valid_sources[0x0e]	4182	1			T2	1		T8	2		T10	1
valid_sources[0x0f]	2189	1			T2	1		T8	2		T10	1
valid_sources[0x10]	2159	1			T7	4		T10	2		T14	23
valid_sources[0x11]	2084	1			T8	2		T10	2		T42	1
valid_sources[0x12]	3064	1			T8	3		T10	3		T42	1
valid_sources[0x13]	2058	1			T7	1		T8	3		T10	5
valid_sources[0x14]	2786	1			T8	2		T10	5		T42	1
valid_sources[0x15]	2245	1			T4	1		T5	1		T8	1
valid_sources[0x16]	2184	1			T7	2		T8	6		T10	2
valid_sources[0x17]	2529	1			T8	2		T10	8		T42	4
valid_sources[0x18]	2152	1			T5	1		T10	7		T42	1
valid_sources[0x19]	4133	1			T5	1		T8	1		T10	4
valid_sources[0x1a]	2103	1			T10	2		T14	22		T39	4
valid_sources[0x1b]	2131	1			T8	4		T10	3		T14	35
valid_sources[0x1c]	2541	1			T5	1		T8	1		T10	10
valid_sources[0x1d]	2091	1			T8	1		T10	1		T42	3
valid_sources[0x1e]	2277	1			T2	1		T5	1		T8	1
valid_sources[0x1f]	2070	1			T8	2		T10	4		T14	45
valid_sources[0x20]	1892	1			T8	1		T9	2		T10	9
valid_sources[0x21]	2428	1			T5	1		T8	1		T14	40
valid_sources[0x22]	1939	1			T4	1		T8	1		T10	6
valid_sources[0x23]	2362	1			T2	2		T8	1		T42	2
valid_sources[0x24]	2100	1			T8	3		T10	3		T14	31
valid_sources[0x25]	2523	1			T7	7		T14	39		T39	11
valid_sources[0x26]	1966	1			T4	2		T8	1		T10	10
valid_sources[0x27]	2161	1			T5	1		T8	4		T14	18
valid_sources[0x28]	2044	1			T10	3		T42	2		T14	36
valid_sources[0x29]	2115	1			T8	1		T10	8		T42	3
valid_sources[0x2a]	5600	1			T8	2		T10	5		T14	32
valid_sources[0x2b]	2066	1			T7	6		T8	1		T10	6
valid_sources[0x2c]	2158	1			T10	2		T42	1		T43	285
valid_sources[0x2d]	2077	1			T4	4		T8	2		T10	8
valid_sources[0x2e]	1976	1			T5	1		T7	2		T8	3
valid_sources[0x2f]	2326	1			T8	5		T10	4		T14	43
valid_sources[0x30]	3481	1			T2	2		T8	2		T10	3
valid_sources[0x31]	3237	1			T8	1		T10	1		T42	1
valid_sources[0x32]	1861	1			T8	2		T10	3		T42	2
valid_sources[0x33]	2944	1			T10	8		T42	1		T14	32
valid_sources[0x34]	2462	1			T5	2		T8	2		T42	4
valid_sources[0x35]	1907	1			T8	1		T10	8		T14	27
valid_sources[0x36]	2313	1			T8	1		T10	7		T14	32
valid_sources[0x37]	2900	1			T5	1		T8	4		T42	6
valid_sources[0x38]	1940	1			T5	2		T10	8		T42	1
valid_sources[0x39]	3413	1			T5	2		T7	2		T8	1
valid_sources[0x3a]	8115	1			T8	2		T10	27		T14	50
valid_sources[0x3b]	2025	1			T8	1		T10	3		T42	1
valid_sources[0x3c]	2177	1			T2	1		T4	1		T7	1
valid_sources[0x3d]	2467	1			T2	1		T7	4		T8	1
valid_sources[0x3e]	2313	1			T4	1		T7	2		T9	1
valid_sources[0x3f]	2661	1			T4	3		T5	2		T10	4
valid_sources[0x40]	2055	1			T5	1		T8	2		T10	1
valid_sources[0x41]	2620	1			T6	477		T8	3		T10	2
valid_sources[0x42]	2070	1			T5	1		T8	1		T14	25
valid_sources[0x43]	2546	1			T5	2		T8	2		T10	1
valid_sources[0x44]	4027	1			T10	4		T14	44		T39	7
valid_sources[0x45]	4154	1			T8	1		T42	3		T14	29
valid_sources[0x46]	2011	1			T4	1		T8	2		T42	1
valid_sources[0x47]	2162	1			T8	1		T10	14		T42	2
valid_sources[0x48]	1893	1			T8	4		T10	5		T42	2
valid_sources[0x49]	2044	1			T5	1		T8	2		T10	10
valid_sources[0x4a]	3227	1			T8	3		T10	1		T14	31
valid_sources[0x4b]	1935	1			T8	4		T14	25		T39	7
valid_sources[0x4c]	5661	1			T7	8		T10	1		T42	1
valid_sources[0x4d]	1943	1			T2	2		T8	2		T10	8
valid_sources[0x4e]	2299	1			T8	1		T10	6		T42	3
valid_sources[0x4f]	3873	1			T10	6		T14	33		T84	2
valid_sources[0x50]	2027	1			T8	1		T10	1		T42	1
valid_sources[0x51]	3251	1			T5	3		T7	4		T8	3
valid_sources[0x52]	8298	1			T5	1		T8	1		T10	8
valid_sources[0x53]	2066	1			T8	6		T10	5		T14	35
valid_sources[0x54]	2514	1			T8	2		T10	4		T14	40
valid_sources[0x55]	2162	1			T8	1		T10	27		T14	33
valid_sources[0x56]	2895	1			T5	1		T8	3		T10	1
valid_sources[0x57]	2068	1			T5	1		T14	32		T39	3
valid_sources[0x58]	2048	1			T8	6		T14	45		T39	5
valid_sources[0x59]	3030	1			T5	1		T7	3		T8	7
valid_sources[0x5a]	1994	1			T7	5		T8	3		T10	2
valid_sources[0x5b]	2227	1			T3	32		T10	7		T42	2
valid_sources[0x5c]	2186	1			T8	2		T42	7		T14	38
valid_sources[0x5d]	2476	1			T8	1		T42	1		T14	44
valid_sources[0x5e]	2053	1			T42	1		T14	32		T84	2
valid_sources[0x5f]	1974	1			T8	3		T10	2		T14	51
valid_sources[0x60]	2146	1			T5	2		T7	13		T8	3
valid_sources[0x61]	2194	1			T5	1		T14	34		T40	5
valid_sources[0x62]	8505	1			T8	2		T10	3		T14	44
valid_sources[0x63]	2322	1			T8	2		T10	7		T14	25
valid_sources[0x64]	3727	1			T5	1		T7	1		T8	1
valid_sources[0x65]	2057	1			T5	2		T8	4		T10	7
valid_sources[0x66]	2408	1			T8	3		T10	7		T14	44
valid_sources[0x67]	1943	1			T8	1		T10	3		T14	36
valid_sources[0x68]	2183	1			T2	2		T8	2		T10	1
valid_sources[0x69]	2244	1			T7	1		T10	8		T14	28
valid_sources[0x6a]	1914	1			T4	1		T5	1		T7	1
valid_sources[0x6b]	3816	1			T7	1		T8	4		T10	11
valid_sources[0x6c]	2562	1			T5	2		T8	1		T10	1
valid_sources[0x6d]	5285	1			T42	1		T14	48		T39	8
valid_sources[0x6e]	2639	1			T4	1		T5	1		T8	2
valid_sources[0x6f]	2209	1			T5	1		T8	1		T10	2
valid_sources[0x70]	1868	1			T4	3		T5	1		T8	3
valid_sources[0x71]	1993	1			T5	1		T8	2		T42	2
valid_sources[0x72]	2070	1			T5	1		T7	10		T8	3
valid_sources[0x73]	2028	1			T7	4		T10	1		T42	1
valid_sources[0x74]	2330	1			T7	3		T8	1		T9	1
valid_sources[0x75]	2366	1			T8	2		T10	6		T42	2
valid_sources[0x76]	3091	1			T5	1		T8	1		T42	5
valid_sources[0x77]	2011	1			T7	6		T10	4		T14	48
valid_sources[0x78]	3091	1			T4	2		T7	3		T8	2
valid_sources[0x79]	2327	1			T10	10		T14	59		T39	7
valid_sources[0x7a]	2181	1			T2	3		T5	1		T8	1
valid_sources[0x7b]	2167	1			T8	2		T10	3		T14	45
valid_sources[0x7c]	2061	1			T7	1		T8	4		T10	4
valid_sources[0x7d]	2047	1			T5	1		T8	2		T10	5
valid_sources[0x7e]	1892	1			T7	1		T14	19		T15	6
valid_sources[0x7f]	2062	1			T4	1		T8	1		T10	7
valid_sources[0x80]	2105	1			T10	4		T42	5		T14	40

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

153318

1

T1

75

T2

8

T3

7

values[0x0]

all_enables

biggest_size

45408

1

T1

17

T2

6

T3

2

values[0x1]

all_enables

biggest_size

25252

1

T1

8

T3

1

T4

5