SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35018 | 1 | T10 | 310 | T39 | 405 | T26 | 306 | ||||
others[1] | 35032 | 1 | T10 | 308 | T39 | 390 | T26 | 299 | ||||
others[2] | 34989 | 1 | T10 | 288 | T39 | 391 | T26 | 309 | ||||
others[3] | 58350 | 1 | T10 | 497 | T39 | 671 | T26 | 487 | ||||
false | 13339 | 1 | T6 | 24 | T10 | 50 | T14 | 138 | ||||
true | 21477 | 1 | T1 | 1 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35163 | 1 | T10 | 292 | T39 | 411 | T26 | 304 | ||||
others[1] | 34977 | 1 | T10 | 310 | T39 | 403 | T26 | 321 | ||||
others[2] | 34561 | 1 | T10 | 305 | T39 | 370 | T26 | 270 | ||||
others[3] | 58686 | 1 | T10 | 493 | T39 | 702 | T26 | 506 | ||||
false | 9271 | 1 | T6 | 12 | T10 | 50 | T14 | 69 | ||||
true | 17462 | 1 | T1 | 1 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 548 | 1 | T14 | 5 | T15 | 2 | T84 | 6 | ||||
others[1] | 563 | 1 | T5 | 1 | T14 | 8 | T84 | 4 | ||||
others[2] | 565 | 1 | T14 | 4 | T15 | 1 | T84 | 6 | ||||
others[3] | 878 | 1 | T5 | 1 | T14 | 4 | T84 | 10 | ||||
false | 9828 | 1 | T1 | 1 | T2 | 5 | T3 | 1 | ||||
true | 2793 | 1 | T5 | 7 | T14 | 37 | T15 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |