Group : pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv



Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 6 0 0.00
Crosses 6 6 0 0.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 2 0 0.00 100 1 1 2
reset_cp 2 2 0 0.00 100 1 1 2
sleep_cp 2 2 0 0.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
reset_cross 6 6 0 0.00 100 1 1 0


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for enable_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable reset_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for reset_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Cross reset_cross

Samples crossed: reset_cp enable_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 6 6 0 0.00 6
Automatically Generated Cross Bins 6 6 0 0.00 6
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for reset_cross

Element holes
reset_cpenable_cpsleep_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] * * -- -- 4
[auto[1]] * [auto[0]] -- -- 2


User Defined Cross Bins for reset_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
illegal 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%