| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 53.15 | 42.44 | 64.05 | 77.73 | 0.00 | 42.18 | 100.00 | 45.66 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 49.03 | 49.03 | 41.88 | 41.88 | 57.77 | 57.77 | 88.59 | 88.59 | 0.00 | 0.00 | 41.03 | 41.03 | 94.10 | 94.10 | 19.80 | 19.80 | /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.325383975 |
| 52.08 | 3.05 | 41.88 | 0.00 | 58.20 | 0.43 | 88.59 | 0.00 | 0.00 | 0.00 | 41.03 | 0.00 | 96.07 | 1.97 | 38.79 | 18.99 | /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3994611561 |
| 53.05 | 0.97 | 42.12 | 0.24 | 58.92 | 0.71 | 89.02 | 0.43 | 0.00 | 0.00 | 41.03 | 0.00 | 96.39 | 0.33 | 43.86 | 5.07 | /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.1438021543 |
| 53.81 | 0.76 | 42.36 | 0.24 | 61.06 | 2.14 | 89.89 | 0.87 | 0.00 | 0.00 | 41.60 | 0.57 | 97.05 | 0.66 | 44.68 | 0.82 | /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.576535804 |
| 54.40 | 0.59 | 42.44 | 0.08 | 61.91 | 0.86 | 89.89 | 0.00 | 0.00 | 0.00 | 42.18 | 0.57 | 99.67 | 2.62 | 44.68 | 0.00 | /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2953785311 |
| 54.69 | 0.29 | 42.44 | 0.00 | 63.62 | 1.71 | 89.89 | 0.00 | 0.00 | 0.00 | 42.18 | 0.00 | 99.67 | 0.00 | 45.01 | 0.33 | /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.2566754270 |
| 54.78 | 0.09 | 42.44 | 0.00 | 63.77 | 0.14 | 89.89 | 0.00 | 0.00 | 0.00 | 42.18 | 0.00 | 99.67 | 0.00 | 45.50 | 0.49 | /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2463265831 |
| 54.83 | 0.05 | 42.44 | 0.00 | 63.77 | 0.00 | 89.89 | 0.00 | 0.00 | 0.00 | 42.18 | 0.00 | 100.00 | 0.33 | 45.50 | 0.00 | /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.4211353867 |
| 54.87 | 0.04 | 42.44 | 0.00 | 63.91 | 0.14 | 89.89 | 0.00 | 0.00 | 0.00 | 42.18 | 0.00 | 100.00 | 0.00 | 45.66 | 0.16 | /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2582902996 |
| 54.89 | 0.02 | 42.44 | 0.00 | 64.05 | 0.14 | 89.89 | 0.00 | 0.00 | 0.00 | 42.18 | 0.00 | 100.00 | 0.00 | 45.66 | 0.00 | /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2991851730 |
| Name |
|---|
| /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.1000812619 |
| /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.935552972 |
| /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.511512246 |
| /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2021165114 |
| /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.2101234428 |
| /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.326304432 |
| /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.4184515542 |
| /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3042197498 |
| /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.4189067031 |
| /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.2785524962 |
| /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.1123973468 |
| /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.12655887 |
| /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2894091270 |
| /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1895325979 |
| /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.3669320339 |
| /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1763108251 |
| /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.520149985 |
| /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.2892728337 |
| /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.1996904145 |
| /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.693608103 |
| /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1405603243 |
| /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3801145165 |
| /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.4204610890 |
| /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3499145354 |
| /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.645335920 |
| /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.2962174599 |
| /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.4078716045 |
| /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2195868139 |
| /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3715299931 |
| /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.3129731436 |
| /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.417686385 |
| /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.2926669346 |
| /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3817893898 |
| /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2622322377 |
| /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.228258594 |
| /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.3115038675 |
| /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3039073188 |
| /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1635862665 |
| /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1577625226 |
| /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.4276390596 |
| /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1158717225 |
| /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.802519903 |
| /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1814972177 |
| /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.527148835 |
| /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.210484430 |
| /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.896956536 |
| /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.443116991 |
| /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.473525055 |
| /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.113656961 |
| /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.1291670792 |
| /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1958687711 |
| /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3596627224 |
| /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3696002258 |
| /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.4199186550 |
| /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3746149288 |
| /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1099523509 |
| /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.3372106837 |
| /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1223786110 |
| /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3898293249 |
| /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.2885385667 |
| /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3277410612 |
| /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.1187199856 |
| /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2180986185 |
| /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2583959196 |
| /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.570056993 |
| /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.2865782487 |
| /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.992992857 |
| /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.3912757305 |
| /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.639121190 |
| /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2379748527 |
| /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.1891585965 |
| /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2222095567 |
| /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.340043066 |
| /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1398280471 |
| /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.343087945 |
| /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.305892585 |
| /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.1961753522 |
| /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1265670911 |
| /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.2377224624 |
| /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1999808779 |
| /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2182123677 |
| /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.4291401864 |
| /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.3466450280 |
| /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.1423247445 |
| /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.548007676 |
| /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.2290071296 |
| /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.771907904 |
| /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.2726907050 |
| /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.2799867403 |
| /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.2806676471 |
| /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.848010213 |
| /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2794464894 |
| /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3629446739 |
| /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.739518798 |
| /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.4216137038 |
| /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.2535013885 |
| /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.648506898 |
| /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3416560298 |
| /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.4258763784 |
| /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2800230386 |
| /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3844211666 |
| /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.2892059132 |
| /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2238084873 |
| /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.61469599 |
| /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3481413976 |
| /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.1623415569 |
| /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.3179857966 |
| /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.1416499694 |
| /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.2555932447 |
| /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.174576462 |
| /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.736143438 |
| /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.4216155078 |
| /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.1975045572 |
| /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.2761959734 |
| /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.4072073666 |
| /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.1297523168 |
| /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.3214623617 |
| /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.2633248325 |
| /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.3391176078 |
| /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.4148271181 |
| /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.797683434 |
| /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.3497062438 |
| /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.1794493379 |
| /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3908410872 |
| /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.4167769858 |
| /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.3129964515 |
| /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1796130021 |
| /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3545132775 |
| /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3575030944 |
| /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3527408554 |
| /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1855160661 |
| /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2035083519 |
| /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.1782702356 |
| /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.421011760 |
| /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1204669373 |
| /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.136753940 |
| /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2242156120 |
| /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.1820134030 |
| /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.688336465 |
| /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2711876304 |
| /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.100860692 |
| /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.652540291 |
| /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1643511120 |
| /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1803315641 |
| /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2568199800 |
| /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.764260430 |
| /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.795247692 |
| /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.983048545 |
| /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1133146580 |
| /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.965456530 |
| /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3196196114 |
| /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.1024489803 |
| /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2919530136 |
| /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.3960797068 |
| /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.331839327 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.2101234428 | Mar 14 12:23:07 PM PDT 24 | Mar 14 12:23:07 PM PDT 24 | 121937749 ps | ||
| T2 | /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.331839327 | Mar 14 12:23:44 PM PDT 24 | Mar 14 12:23:47 PM PDT 24 | 56612507 ps | ||
| T3 | /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.1024489803 | Mar 14 12:23:44 PM PDT 24 | Mar 14 12:23:45 PM PDT 24 | 42742837 ps | ||
| T8 | /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.4072073666 | Mar 14 12:22:26 PM PDT 24 | Mar 14 12:22:27 PM PDT 24 | 24515706 ps | ||
| T7 | /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.570056993 | Mar 14 12:23:46 PM PDT 24 | Mar 14 12:23:50 PM PDT 24 | 112547169 ps | ||
| T4 | /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.576535804 | Mar 14 12:24:02 PM PDT 24 | Mar 14 12:24:03 PM PDT 24 | 223225849 ps | ||
| T12 | /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3817893898 | Mar 14 12:23:41 PM PDT 24 | Mar 14 12:23:42 PM PDT 24 | 25490855 ps | ||
| T5 | /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.325383975 | Mar 14 12:22:34 PM PDT 24 | Mar 14 12:22:35 PM PDT 24 | 77823263 ps | ||
| T9 | /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.2726907050 | Mar 14 12:23:36 PM PDT 24 | Mar 14 12:23:37 PM PDT 24 | 20235864 ps | ||
| T13 | /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.4211353867 | Mar 14 12:23:29 PM PDT 24 | Mar 14 12:23:30 PM PDT 24 | 32349940 ps | ||
| T21 | /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.764260430 | Mar 14 12:22:04 PM PDT 24 | Mar 14 12:22:05 PM PDT 24 | 29175350 ps | ||
| T10 | /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3844211666 | Mar 14 12:23:39 PM PDT 24 | Mar 14 12:23:40 PM PDT 24 | 19795117 ps | ||
| T11 | /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3481413976 | Mar 14 12:23:38 PM PDT 24 | Mar 14 12:23:39 PM PDT 24 | 15963887 ps | ||
| T45 | /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.1975045572 | Mar 14 12:21:14 PM PDT 24 | Mar 14 12:21:15 PM PDT 24 | 16822566 ps | ||
| T48 | /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.1438021543 | Mar 14 12:23:20 PM PDT 24 | Mar 14 12:23:21 PM PDT 24 | 34208296 ps | ||
| T6 | /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3746149288 | Mar 14 12:21:19 PM PDT 24 | Mar 14 12:21:20 PM PDT 24 | 113429258 ps | ||
| T49 | /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.2761959734 | Mar 14 12:24:17 PM PDT 24 | Mar 14 12:24:18 PM PDT 24 | 30713226 ps | ||
| T14 | /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3042197498 | Mar 14 12:24:43 PM PDT 24 | Mar 14 12:24:45 PM PDT 24 | 199946627 ps | ||
| T15 | /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.2926669346 | Mar 14 12:23:43 PM PDT 24 | Mar 14 12:23:44 PM PDT 24 | 121073411 ps | ||
| T23 | /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3499145354 | Mar 14 12:24:02 PM PDT 24 | Mar 14 12:24:03 PM PDT 24 | 30441675 ps | ||
| T47 | /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.340043066 | Mar 14 12:20:35 PM PDT 24 | Mar 14 12:20:38 PM PDT 24 | 296522085 ps | ||
| T24 | /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2953785311 | Mar 14 12:19:58 PM PDT 24 | Mar 14 12:19:59 PM PDT 24 | 28401813 ps | ||
| T39 | /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2180986185 | Mar 14 12:22:37 PM PDT 24 | Mar 14 12:22:38 PM PDT 24 | 17829303 ps | ||
| T40 | /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3527408554 | Mar 14 12:24:29 PM PDT 24 | Mar 14 12:24:30 PM PDT 24 | 17636061 ps | ||
| T41 | /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3696002258 | Mar 14 12:23:43 PM PDT 24 | Mar 14 12:23:44 PM PDT 24 | 39374885 ps | ||
| T42 | /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2242156120 | Mar 14 12:24:02 PM PDT 24 | Mar 14 12:24:03 PM PDT 24 | 81083433 ps | ||
| T16 | /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.2566754270 | Mar 14 12:21:28 PM PDT 24 | Mar 14 12:21:30 PM PDT 24 | 138627093 ps | ||
| T43 | /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3994611561 | Mar 14 12:20:47 PM PDT 24 | Mar 14 12:20:51 PM PDT 24 | 330446944 ps | ||
| T17 | /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.527148835 | Mar 14 12:21:19 PM PDT 24 | Mar 14 12:21:20 PM PDT 24 | 127009810 ps | ||
| T44 | /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3596627224 | Mar 14 12:22:07 PM PDT 24 | Mar 14 12:22:08 PM PDT 24 | 41463352 ps | ||
| T18 | /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.3669320339 | Mar 14 12:24:03 PM PDT 24 | Mar 14 12:24:04 PM PDT 24 | 63416762 ps | ||
| T69 | /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.305892585 | Mar 14 12:19:27 PM PDT 24 | Mar 14 12:19:28 PM PDT 24 | 19102651 ps | ||
| T19 | /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2894091270 | Mar 14 12:24:55 PM PDT 24 | Mar 14 12:24:58 PM PDT 24 | 84971103 ps | ||
| T46 | /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2379748527 | Mar 14 12:21:48 PM PDT 24 | Mar 14 12:21:49 PM PDT 24 | 72205456 ps | ||
| T22 | /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.417686385 | Mar 14 12:24:02 PM PDT 24 | Mar 14 12:24:03 PM PDT 24 | 295158110 ps | ||
| T53 | /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1999808779 | Mar 14 12:23:56 PM PDT 24 | Mar 14 12:23:57 PM PDT 24 | 874117855 ps | ||
| T20 | /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.343087945 | Mar 14 12:21:11 PM PDT 24 | Mar 14 12:21:12 PM PDT 24 | 39238798 ps | ||
| T25 | /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.2535013885 | Mar 14 12:19:10 PM PDT 24 | Mar 14 12:19:11 PM PDT 24 | 58159324 ps | ||
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| T71 | /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1796130021 | Mar 14 12:22:11 PM PDT 24 | Mar 14 12:22:12 PM PDT 24 | 54442887 ps | ||
| T72 | /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3801145165 | Mar 14 12:23:36 PM PDT 24 | Mar 14 12:23:37 PM PDT 24 | 126535152 ps | ||
| T26 | /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.2892728337 | Mar 14 12:24:02 PM PDT 24 | Mar 14 12:24:03 PM PDT 24 | 71391503 ps | ||
| T27 | /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.2785524962 | Mar 14 12:23:56 PM PDT 24 | Mar 14 12:23:57 PM PDT 24 | 43204925 ps | ||
| T73 | /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.4216155078 | Mar 14 12:20:53 PM PDT 24 | Mar 14 12:20:54 PM PDT 24 | 58067798 ps | ||
| T59 | /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.1961753522 | Mar 14 12:24:21 PM PDT 24 | Mar 14 12:24:22 PM PDT 24 | 20354537 ps | ||
| T58 | /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.1891585965 | Mar 14 12:22:25 PM PDT 24 | Mar 14 12:22:28 PM PDT 24 | 160627608 ps | ||
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| T74 | /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2568199800 | Mar 14 12:23:46 PM PDT 24 | Mar 14 12:23:47 PM PDT 24 | 58038729 ps | ||
| T75 | /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2195868139 | Mar 14 12:23:36 PM PDT 24 | Mar 14 12:23:37 PM PDT 24 | 48352512 ps | ||
| T60 | /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.648506898 | Mar 14 12:21:53 PM PDT 24 | Mar 14 12:21:54 PM PDT 24 | 891135846 ps | ||
| T28 | /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.983048545 | Mar 14 12:23:45 PM PDT 24 | Mar 14 12:23:47 PM PDT 24 | 41824588 ps | ||
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| T76 | /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.1123973468 | Mar 14 12:22:37 PM PDT 24 | Mar 14 12:22:38 PM PDT 24 | 21715188 ps | ||
| T29 | /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.935552972 | Mar 14 12:23:18 PM PDT 24 | Mar 14 12:23:21 PM PDT 24 | 151617425 ps | ||
| T77 | /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3196196114 | Mar 14 12:23:45 PM PDT 24 | Mar 14 12:23:47 PM PDT 24 | 36404101 ps | ||
| T78 | /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.802519903 | Mar 14 12:23:41 PM PDT 24 | Mar 14 12:23:43 PM PDT 24 | 54597826 ps | ||
| T30 | /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1577625226 | Mar 14 12:21:57 PM PDT 24 | Mar 14 12:21:58 PM PDT 24 | 34602771 ps | ||
| T62 | /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.992992857 | Mar 14 12:23:47 PM PDT 24 | Mar 14 12:23:50 PM PDT 24 | 48186381 ps | ||
| T79 | /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3277410612 | Mar 14 12:21:42 PM PDT 24 | Mar 14 12:21:44 PM PDT 24 | 107311535 ps | ||
| T80 | /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.3115038675 | Mar 14 12:23:36 PM PDT 24 | Mar 14 12:23:39 PM PDT 24 | 82423918 ps | ||
| T63 | /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3898293249 | Mar 14 12:21:42 PM PDT 24 | Mar 14 12:21:44 PM PDT 24 | 31299125 ps | ||
| T31 | /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2222095567 | Mar 14 12:23:33 PM PDT 24 | Mar 14 12:23:34 PM PDT 24 | 26389205 ps | ||
| T64 | /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.4199186550 | Mar 14 12:23:41 PM PDT 24 | Mar 14 12:23:43 PM PDT 24 | 64348240 ps | ||
| T81 | /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.4184515542 | Mar 14 12:23:26 PM PDT 24 | Mar 14 12:23:26 PM PDT 24 | 44169239 ps | ||
| T82 | /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.2290071296 | Mar 14 12:21:51 PM PDT 24 | Mar 14 12:21:52 PM PDT 24 | 23781891 ps | ||
| T83 | /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.1187199856 | Mar 14 12:23:36 PM PDT 24 | Mar 14 12:23:37 PM PDT 24 | 44756516 ps | ||
| T84 | /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.443116991 | Mar 14 12:22:21 PM PDT 24 | Mar 14 12:22:22 PM PDT 24 | 51994330 ps | ||
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| T86 | /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.12655887 | Mar 14 12:24:06 PM PDT 24 | Mar 14 12:24:08 PM PDT 24 | 31682221 ps | ||
| T37 | /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1763108251 | Mar 14 12:22:26 PM PDT 24 | Mar 14 12:22:27 PM PDT 24 | 39292009 ps | ||
| T87 | /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2991851730 | Mar 14 12:23:29 PM PDT 24 | Mar 14 12:23:30 PM PDT 24 | 39697715 ps | ||
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| T90 | /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.4258763784 | Mar 14 12:23:36 PM PDT 24 | Mar 14 12:23:37 PM PDT 24 | 19378711 ps | ||
| T91 | /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.1996904145 | Mar 14 12:23:46 PM PDT 24 | Mar 14 12:23:49 PM PDT 24 | 83479842 ps | ||
| T54 | /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.736143438 | Mar 14 12:23:47 PM PDT 24 | Mar 14 12:23:49 PM PDT 24 | 23777601 ps | ||
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| T94 | /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1099523509 | Mar 14 12:23:47 PM PDT 24 | Mar 14 12:23:50 PM PDT 24 | 103742880 ps | ||
| T95 | /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2711876304 | Mar 14 12:21:46 PM PDT 24 | Mar 14 12:21:47 PM PDT 24 | 51210683 ps | ||
| T66 | /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3039073188 | Mar 14 12:24:02 PM PDT 24 | Mar 14 12:24:04 PM PDT 24 | 109944697 ps | ||
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| T97 | /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3545132775 | Mar 14 12:21:55 PM PDT 24 | Mar 14 12:21:57 PM PDT 24 | 48368175 ps | ||
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| T99 | /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.3372106837 | Mar 14 12:21:34 PM PDT 24 | Mar 14 12:21:35 PM PDT 24 | 43836928 ps | ||
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| T101 | /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.4078716045 | Mar 14 12:23:36 PM PDT 24 | Mar 14 12:23:37 PM PDT 24 | 64976877 ps | ||
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| T103 | /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2021165114 | Mar 14 12:24:56 PM PDT 24 | Mar 14 12:24:57 PM PDT 24 | 80228375 ps | ||
| T104 | /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.2892059132 | Mar 14 12:21:58 PM PDT 24 | Mar 14 12:21:58 PM PDT 24 | 24843176 ps | ||
| T105 | /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1405603243 | Mar 14 12:24:02 PM PDT 24 | Mar 14 12:24:04 PM PDT 24 | 131350338 ps | ||
| T106 | /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.3960797068 | Mar 14 12:23:46 PM PDT 24 | Mar 14 12:23:47 PM PDT 24 | 23278031 ps | ||
| T107 | /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.228258594 | Mar 14 12:23:43 PM PDT 24 | Mar 14 12:23:44 PM PDT 24 | 31491576 ps | ||
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| T111 | /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1643511120 | Mar 14 12:24:02 PM PDT 24 | Mar 14 12:24:03 PM PDT 24 | 31412807 ps | ||
| T112 | /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1803315641 | Mar 14 12:24:03 PM PDT 24 | Mar 14 12:24:04 PM PDT 24 | 56400572 ps | ||
| T113 | /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1223786110 | Mar 14 12:22:20 PM PDT 24 | Mar 14 12:22:21 PM PDT 24 | 40459267 ps | ||
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| T115 | /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.652540291 | Mar 14 12:20:57 PM PDT 24 | Mar 14 12:20:58 PM PDT 24 | 18306427 ps | ||
| T116 | /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1958687711 | Mar 14 12:21:42 PM PDT 24 | Mar 14 12:21:43 PM PDT 24 | 95096314 ps | ||
| T117 | /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.4276390596 | Mar 14 12:23:44 PM PDT 24 | Mar 14 12:23:44 PM PDT 24 | 71676190 ps | ||
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| T119 | /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.3912757305 | Mar 14 12:23:45 PM PDT 24 | Mar 14 12:23:47 PM PDT 24 | 42947488 ps | ||
| T32 | /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.848010213 | Mar 14 12:24:05 PM PDT 24 | Mar 14 12:24:06 PM PDT 24 | 90571588 ps | ||
| T33 | /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3575030944 | Mar 14 12:23:45 PM PDT 24 | Mar 14 12:23:47 PM PDT 24 | 41369345 ps | ||
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| T120 | /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.473525055 | Mar 14 12:23:43 PM PDT 24 | Mar 14 12:23:46 PM PDT 24 | 51780224 ps | ||
| T121 | /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.4216137038 | Mar 14 12:20:18 PM PDT 24 | Mar 14 12:20:19 PM PDT 24 | 30316405 ps | ||
| T122 | /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2583959196 | Mar 14 12:21:33 PM PDT 24 | Mar 14 12:21:35 PM PDT 24 | 39850749 ps | ||
| T123 | /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.421011760 | Mar 14 12:23:45 PM PDT 24 | Mar 14 12:23:47 PM PDT 24 | 41879215 ps | ||
| T124 | /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.1291670792 | Mar 14 12:21:27 PM PDT 24 | Mar 14 12:21:28 PM PDT 24 | 58298500 ps | ||
| T35 | /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.1000812619 | Mar 14 12:24:56 PM PDT 24 | Mar 14 12:24:57 PM PDT 24 | 131827486 ps | ||
| T125 | /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2919530136 | Mar 14 12:24:03 PM PDT 24 | Mar 14 12:24:03 PM PDT 24 | 20071770 ps | ||
| T126 | /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1855160661 | Mar 14 12:23:46 PM PDT 24 | Mar 14 12:23:47 PM PDT 24 | 125754496 ps | ||
| T127 | /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2800230386 | Mar 14 12:23:37 PM PDT 24 | Mar 14 12:23:39 PM PDT 24 | 63237973 ps | ||
| T128 | /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.2799867403 | Mar 14 12:24:55 PM PDT 24 | Mar 14 12:24:57 PM PDT 24 | 21955715 ps | ||
| T129 | /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.548007676 | Mar 14 12:23:46 PM PDT 24 | Mar 14 12:23:47 PM PDT 24 | 130271402 ps | ||
| T130 | /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.688336465 | Mar 14 12:20:54 PM PDT 24 | Mar 14 12:20:56 PM PDT 24 | 200025213 ps | ||
| T131 | /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2794464894 | Mar 14 12:23:27 PM PDT 24 | Mar 14 12:23:29 PM PDT 24 | 256937453 ps | ||
| T132 | /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.693608103 | Mar 14 12:22:37 PM PDT 24 | Mar 14 12:22:38 PM PDT 24 | 260593608 ps | ||
| T56 | /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2582902996 | Mar 14 12:23:45 PM PDT 24 | Mar 14 12:23:47 PM PDT 24 | 110256948 ps | ||
| T133 | /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.4204610890 | Mar 14 12:24:02 PM PDT 24 | Mar 14 12:24:03 PM PDT 24 | 17624938 ps | ||
| T51 | /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2463265831 | Mar 14 12:23:46 PM PDT 24 | Mar 14 12:23:51 PM PDT 24 | 275365586 ps | ||
| T134 | /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.1297523168 | Mar 14 12:21:51 PM PDT 24 | Mar 14 12:21:54 PM PDT 24 | 262182286 ps | ||
| T135 | /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.795247692 | Mar 14 12:24:03 PM PDT 24 | Mar 14 12:24:03 PM PDT 24 | 26559566 ps | ||
| T136 | /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.520149985 | Mar 14 12:24:03 PM PDT 24 | Mar 14 12:24:04 PM PDT 24 | 37240856 ps | ||
| T55 | /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3629446739 | Mar 14 12:23:48 PM PDT 24 | Mar 14 12:23:50 PM PDT 24 | 74367650 ps | ||
| T137 | /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.326304432 | Mar 14 12:23:26 PM PDT 24 | Mar 14 12:23:27 PM PDT 24 | 41540621 ps | ||
| T138 | /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1158717225 | Mar 14 12:22:07 PM PDT 24 | Mar 14 12:22:08 PM PDT 24 | 103634380 ps | ||
| T67 | /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.965456530 | Mar 14 12:23:46 PM PDT 24 | Mar 14 12:23:47 PM PDT 24 | 239863968 ps | ||
| T139 | /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.1794493379 | Mar 14 12:23:46 PM PDT 24 | Mar 14 12:23:47 PM PDT 24 | 128568525 ps | ||
| T140 | /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.2377224624 | Mar 14 12:19:27 PM PDT 24 | Mar 14 12:19:30 PM PDT 24 | 93306088 ps | ||
| T141 | /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.2962174599 | Mar 14 12:23:36 PM PDT 24 | Mar 14 12:23:37 PM PDT 24 | 102407784 ps | ||
| T65 | /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.511512246 | Mar 14 12:23:19 PM PDT 24 | Mar 14 12:23:20 PM PDT 24 | 43400980 ps | ||
| T57 | /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.4189067031 | Mar 14 12:19:48 PM PDT 24 | Mar 14 12:19:49 PM PDT 24 | 1529045005 ps | ||
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| T143 | /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.2885385667 | Mar 14 12:22:09 PM PDT 24 | Mar 14 12:22:10 PM PDT 24 | 561346769 ps | ||
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| T145 | /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1265670911 | Mar 14 12:20:35 PM PDT 24 | Mar 14 12:20:36 PM PDT 24 | 25555829 ps | ||
| T146 | /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1895325979 | Mar 14 12:23:34 PM PDT 24 | Mar 14 12:23:35 PM PDT 24 | 250217280 ps | ||
| T147 | /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3715299931 | Mar 14 12:21:19 PM PDT 24 | Mar 14 12:21:20 PM PDT 24 | 99536063 ps | ||
| T148 | /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.136753940 | Mar 14 12:24:01 PM PDT 24 | Mar 14 12:24:02 PM PDT 24 | 55345209 ps | ||
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| T150 | /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.113656961 | Mar 14 12:22:09 PM PDT 24 | Mar 14 12:22:11 PM PDT 24 | 229661165 ps | ||
| T36 | /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.739518798 | Mar 14 12:22:10 PM PDT 24 | Mar 14 12:22:10 PM PDT 24 | 41851508 ps | ||
| T151 | /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1635862665 | Mar 14 12:23:43 PM PDT 24 | Mar 14 12:23:44 PM PDT 24 | 88434532 ps | ||
| T152 | /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1398280471 | Mar 14 12:23:41 PM PDT 24 | Mar 14 12:23:42 PM PDT 24 | 25936736 ps | ||
| T153 | /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.1782702356 | Mar 14 12:24:14 PM PDT 24 | Mar 14 12:24:16 PM PDT 24 | 200178156 ps | ||
| T154 | /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2182123677 | Mar 14 12:24:18 PM PDT 24 | Mar 14 12:24:19 PM PDT 24 | 21276203 ps | ||
| T155 | /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1814972177 | Mar 14 12:22:09 PM PDT 24 | Mar 14 12:22:10 PM PDT 24 | 127977735 ps | ||
| T156 | /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.100860692 | Mar 14 12:24:02 PM PDT 24 | Mar 14 12:24:03 PM PDT 24 | 29537709 ps | ||
| T157 | /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2238084873 | Mar 14 12:23:38 PM PDT 24 | Mar 14 12:23:39 PM PDT 24 | 37214778 ps | ||
| T68 | /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3416560298 | Mar 14 12:22:00 PM PDT 24 | Mar 14 12:22:01 PM PDT 24 | 153135655 ps | ||
| T158 | /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.3179857966 | Mar 14 12:24:58 PM PDT 24 | Mar 14 12:24:59 PM PDT 24 | 16580347 ps | ||
| T159 | /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3908410872 | Mar 14 12:24:43 PM PDT 24 | Mar 14 12:24:44 PM PDT 24 | 35093332 ps | ||
| T38 | /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.210484430 | Mar 14 12:23:41 PM PDT 24 | Mar 14 12:23:42 PM PDT 24 | 49177301 ps | ||
| T160 | /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.1416499694 | Mar 14 12:21:58 PM PDT 24 | Mar 14 12:21:58 PM PDT 24 | 28252073 ps | ||
| T161 | /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.174576462 | Mar 14 12:24:29 PM PDT 24 | Mar 14 12:24:33 PM PDT 24 | 1515561346 ps | ||
| T162 | /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.3214623617 | Mar 14 12:23:31 PM PDT 24 | Mar 14 12:23:33 PM PDT 24 | 147723158 ps | ||
| T163 | /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.797683434 | Mar 14 12:22:04 PM PDT 24 | Mar 14 12:22:05 PM PDT 24 | 22535145 ps | ||
| T164 | /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.2555932447 | Mar 14 12:24:29 PM PDT 24 | Mar 14 12:24:31 PM PDT 24 | 146022310 ps | ||
| T165 | /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.4291401864 | Mar 14 12:23:20 PM PDT 24 | Mar 14 12:23:21 PM PDT 24 | 44960582 ps | ||
| T52 | /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.2865782487 | Mar 14 12:22:21 PM PDT 24 | Mar 14 12:22:22 PM PDT 24 | 256300688 ps |
| Test location | /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.325383975 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 77823263 ps |
| CPU time | 1.04 seconds |
| Started | Mar 14 12:22:34 PM PDT 24 |
| Finished | Mar 14 12:22:35 PM PDT 24 |
| Peak memory | 195836 kb |
| Host | smart-e2e71fc4-f20f-4365-b47f-dd7a5b6861b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325383975 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.325383975 |
| Directory | /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3994611561 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 330446944 ps |
| CPU time | 3.53 seconds |
| Started | Mar 14 12:20:47 PM PDT 24 |
| Finished | Mar 14 12:20:51 PM PDT 24 |
| Peak memory | 195776 kb |
| Host | smart-74be0eb3-32ea-40f7-955c-a02ce08e7792 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994611561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.3 994611561 |
| Directory | /workspace/1.pwrmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.1438021543 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 34208296 ps |
| CPU time | 0.65 seconds |
| Started | Mar 14 12:23:20 PM PDT 24 |
| Finished | Mar 14 12:23:21 PM PDT 24 |
| Peak memory | 193948 kb |
| Host | smart-1f376594-18e6-43c7-ba50-4e10b4020526 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438021543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.1438021543 |
| Directory | /workspace/12.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.576535804 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 223225849 ps |
| CPU time | 1.03 seconds |
| Started | Mar 14 12:24:02 PM PDT 24 |
| Finished | Mar 14 12:24:03 PM PDT 24 |
| Peak memory | 195596 kb |
| Host | smart-e439496f-2184-44b5-b7d0-394f968b5d9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576535804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err. 576535804 |
| Directory | /workspace/7.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2953785311 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 28401813 ps |
| CPU time | 0.66 seconds |
| Started | Mar 14 12:19:58 PM PDT 24 |
| Finished | Mar 14 12:19:59 PM PDT 24 |
| Peak memory | 195708 kb |
| Host | smart-076df69c-a86b-4253-aa78-d061870dd10c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953785311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.2 953785311 |
| Directory | /workspace/1.pwrmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.2566754270 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 138627093 ps |
| CPU time | 1.96 seconds |
| Started | Mar 14 12:21:28 PM PDT 24 |
| Finished | Mar 14 12:21:30 PM PDT 24 |
| Peak memory | 197076 kb |
| Host | smart-c2f33d97-72f7-4a3a-8712-934c907e8fd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566754270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.2566754270 |
| Directory | /workspace/17.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2463265831 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 275365586 ps |
| CPU time | 1.64 seconds |
| Started | Mar 14 12:23:46 PM PDT 24 |
| Finished | Mar 14 12:23:51 PM PDT 24 |
| Peak memory | 199328 kb |
| Host | smart-8ebd687c-bac9-4bd1-9c62-60d6ac9a2864 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463265831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er r.2463265831 |
| Directory | /workspace/19.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.4211353867 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 32349940 ps |
| CPU time | 0.67 seconds |
| Started | Mar 14 12:23:29 PM PDT 24 |
| Finished | Mar 14 12:23:30 PM PDT 24 |
| Peak memory | 194812 kb |
| Host | smart-0dbb4348-9289-48bb-b851-1673ed96d074 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211353867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.4211353867 |
| Directory | /workspace/1.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2582902996 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 110256948 ps |
| CPU time | 1.12 seconds |
| Started | Mar 14 12:23:45 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 200564 kb |
| Host | smart-425b1b8a-4f99-4ea9-a398-6ee7af2ae0f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582902996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err .2582902996 |
| Directory | /workspace/9.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2991851730 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 39697715 ps |
| CPU time | 0.96 seconds |
| Started | Mar 14 12:23:29 PM PDT 24 |
| Finished | Mar 14 12:23:30 PM PDT 24 |
| Peak memory | 194040 kb |
| Host | smart-57278fc8-a426-40ce-996a-ef8c97fc8de8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991851730 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.2991851730 |
| Directory | /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.1000812619 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 131827486 ps |
| CPU time | 0.94 seconds |
| Started | Mar 14 12:24:56 PM PDT 24 |
| Finished | Mar 14 12:24:57 PM PDT 24 |
| Peak memory | 195292 kb |
| Host | smart-dc4edc07-d9d3-49b3-a3af-003a8e8498fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000812619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.1 000812619 |
| Directory | /workspace/0.pwrmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.935552972 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 151617425 ps |
| CPU time | 1.96 seconds |
| Started | Mar 14 12:23:18 PM PDT 24 |
| Finished | Mar 14 12:23:21 PM PDT 24 |
| Peak memory | 193984 kb |
| Host | smart-29911c50-691b-4d1c-8d2e-324367e771b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935552972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.935552972 |
| Directory | /workspace/0.pwrmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.511512246 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 43400980 ps |
| CPU time | 0.65 seconds |
| Started | Mar 14 12:23:19 PM PDT 24 |
| Finished | Mar 14 12:23:20 PM PDT 24 |
| Peak memory | 195264 kb |
| Host | smart-c97a58ed-919c-4e3a-b8b7-4a4d7a54de90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511512246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.511512246 |
| Directory | /workspace/0.pwrmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2021165114 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 80228375 ps |
| CPU time | 0.85 seconds |
| Started | Mar 14 12:24:56 PM PDT 24 |
| Finished | Mar 14 12:24:57 PM PDT 24 |
| Peak memory | 195400 kb |
| Host | smart-b628c2a5-4e6f-4506-baa1-75ae80c6ba98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021165114 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.2021165114 |
| Directory | /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.2101234428 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 121937749 ps |
| CPU time | 0.67 seconds |
| Started | Mar 14 12:23:07 PM PDT 24 |
| Finished | Mar 14 12:23:07 PM PDT 24 |
| Peak memory | 195772 kb |
| Host | smart-1f356650-5665-40f6-9cc4-b096db035002 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101234428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.2101234428 |
| Directory | /workspace/0.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.326304432 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 41540621 ps |
| CPU time | 0.63 seconds |
| Started | Mar 14 12:23:26 PM PDT 24 |
| Finished | Mar 14 12:23:27 PM PDT 24 |
| Peak memory | 194652 kb |
| Host | smart-8f832889-22de-4124-b0f6-ecb83192472b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326304432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.326304432 |
| Directory | /workspace/0.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.4184515542 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 44169239 ps |
| CPU time | 0.87 seconds |
| Started | Mar 14 12:23:26 PM PDT 24 |
| Finished | Mar 14 12:23:26 PM PDT 24 |
| Peak memory | 195324 kb |
| Host | smart-e1886c40-cd24-4c94-a623-5e904614c431 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184515542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa me_csr_outstanding.4184515542 |
| Directory | /workspace/0.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3042197498 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 199946627 ps |
| CPU time | 2.2 seconds |
| Started | Mar 14 12:24:43 PM PDT 24 |
| Finished | Mar 14 12:24:45 PM PDT 24 |
| Peak memory | 196840 kb |
| Host | smart-d58203f4-92f4-43b1-82aa-873fa26c50a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042197498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.3042197498 |
| Directory | /workspace/0.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.4189067031 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1529045005 ps |
| CPU time | 1.77 seconds |
| Started | Mar 14 12:19:48 PM PDT 24 |
| Finished | Mar 14 12:19:49 PM PDT 24 |
| Peak memory | 201112 kb |
| Host | smart-3c6f03d5-f045-4ffc-af7a-de39d3145269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189067031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err .4189067031 |
| Directory | /workspace/0.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.2785524962 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 43204925 ps |
| CPU time | 0.88 seconds |
| Started | Mar 14 12:23:56 PM PDT 24 |
| Finished | Mar 14 12:23:57 PM PDT 24 |
| Peak memory | 199352 kb |
| Host | smart-839a955a-ce3f-4a08-9847-37eeeeae4b45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785524962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.2 785524962 |
| Directory | /workspace/1.pwrmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.1123973468 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 21715188 ps |
| CPU time | 0.68 seconds |
| Started | Mar 14 12:22:37 PM PDT 24 |
| Finished | Mar 14 12:22:38 PM PDT 24 |
| Peak memory | 195672 kb |
| Host | smart-1206cf62-3710-4581-a1c8-9154bafb4dd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123973468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.1123973468 |
| Directory | /workspace/1.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.12655887 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 31682221 ps |
| CPU time | 0.86 seconds |
| Started | Mar 14 12:24:06 PM PDT 24 |
| Finished | Mar 14 12:24:08 PM PDT 24 |
| Peak memory | 194584 kb |
| Host | smart-d34a5b15-0c51-4d2d-a620-5df01e969519 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12655887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmg r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_same _csr_outstanding.12655887 |
| Directory | /workspace/1.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2894091270 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 84971103 ps |
| CPU time | 1.74 seconds |
| Started | Mar 14 12:24:55 PM PDT 24 |
| Finished | Mar 14 12:24:58 PM PDT 24 |
| Peak memory | 194872 kb |
| Host | smart-608092b5-72ae-443e-934f-c49a7e8c012c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894091270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.2894091270 |
| Directory | /workspace/1.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1895325979 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 250217280 ps |
| CPU time | 1.03 seconds |
| Started | Mar 14 12:23:34 PM PDT 24 |
| Finished | Mar 14 12:23:35 PM PDT 24 |
| Peak memory | 195884 kb |
| Host | smart-4ea96853-54a9-4ad4-9c60-4664396cb65d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895325979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err .1895325979 |
| Directory | /workspace/1.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.3669320339 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 63416762 ps |
| CPU time | 1.05 seconds |
| Started | Mar 14 12:24:03 PM PDT 24 |
| Finished | Mar 14 12:24:04 PM PDT 24 |
| Peak memory | 195532 kb |
| Host | smart-13d09f7d-7aed-41f2-bc37-02c312836eaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669320339 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.3669320339 |
| Directory | /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1763108251 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 39292009 ps |
| CPU time | 0.64 seconds |
| Started | Mar 14 12:22:26 PM PDT 24 |
| Finished | Mar 14 12:22:27 PM PDT 24 |
| Peak memory | 197860 kb |
| Host | smart-0a0edf77-9477-4412-8101-be02b099ed3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763108251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.1763108251 |
| Directory | /workspace/10.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.520149985 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 37240856 ps |
| CPU time | 0.63 seconds |
| Started | Mar 14 12:24:03 PM PDT 24 |
| Finished | Mar 14 12:24:04 PM PDT 24 |
| Peak memory | 195460 kb |
| Host | smart-2fa03ad7-cc83-4c5b-93f7-d699064725db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520149985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.520149985 |
| Directory | /workspace/10.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.2892728337 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 71391503 ps |
| CPU time | 0.83 seconds |
| Started | Mar 14 12:24:02 PM PDT 24 |
| Finished | Mar 14 12:24:03 PM PDT 24 |
| Peak memory | 200428 kb |
| Host | smart-5b522cc3-f6dc-433f-96ef-9cd73b936a86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892728337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s ame_csr_outstanding.2892728337 |
| Directory | /workspace/10.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.1996904145 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 83479842 ps |
| CPU time | 1.58 seconds |
| Started | Mar 14 12:23:46 PM PDT 24 |
| Finished | Mar 14 12:23:49 PM PDT 24 |
| Peak memory | 200772 kb |
| Host | smart-03af3b38-3f79-4e40-b9b2-a0b35ce7fd21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996904145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.1996904145 |
| Directory | /workspace/10.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.693608103 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 260593608 ps |
| CPU time | 1.15 seconds |
| Started | Mar 14 12:22:37 PM PDT 24 |
| Finished | Mar 14 12:22:38 PM PDT 24 |
| Peak memory | 195780 kb |
| Host | smart-a8cdda8f-0314-4832-90b3-9154d61eb808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693608103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err .693608103 |
| Directory | /workspace/10.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1405603243 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 131350338 ps |
| CPU time | 1.36 seconds |
| Started | Mar 14 12:24:02 PM PDT 24 |
| Finished | Mar 14 12:24:04 PM PDT 24 |
| Peak memory | 198432 kb |
| Host | smart-2e509e5d-dc64-4b73-8840-7113e7b6711f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405603243 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.1405603243 |
| Directory | /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3801145165 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 126535152 ps |
| CPU time | 0.65 seconds |
| Started | Mar 14 12:23:36 PM PDT 24 |
| Finished | Mar 14 12:23:37 PM PDT 24 |
| Peak memory | 197760 kb |
| Host | smart-5e9a05d7-7649-45e6-82b8-b9f65d8c08ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801145165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.3801145165 |
| Directory | /workspace/11.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.4204610890 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 17624938 ps |
| CPU time | 0.66 seconds |
| Started | Mar 14 12:24:02 PM PDT 24 |
| Finished | Mar 14 12:24:03 PM PDT 24 |
| Peak memory | 195440 kb |
| Host | smart-c1dfcdf2-69a5-41fe-a90d-356f5da29aad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204610890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.4204610890 |
| Directory | /workspace/11.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3499145354 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 30441675 ps |
| CPU time | 0.9 seconds |
| Started | Mar 14 12:24:02 PM PDT 24 |
| Finished | Mar 14 12:24:03 PM PDT 24 |
| Peak memory | 198820 kb |
| Host | smart-b17c4dc7-0835-418e-b22f-21dc2fa779f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499145354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s ame_csr_outstanding.3499145354 |
| Directory | /workspace/11.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.645335920 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 262994971 ps |
| CPU time | 1.66 seconds |
| Started | Mar 14 12:22:27 PM PDT 24 |
| Finished | Mar 14 12:22:29 PM PDT 24 |
| Peak memory | 196892 kb |
| Host | smart-56d200e7-1327-415e-aade-7586d20d5e1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645335920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.645335920 |
| Directory | /workspace/11.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.2962174599 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 102407784 ps |
| CPU time | 1.1 seconds |
| Started | Mar 14 12:23:36 PM PDT 24 |
| Finished | Mar 14 12:23:37 PM PDT 24 |
| Peak memory | 195772 kb |
| Host | smart-bff8cbe4-bf7d-4883-8e7b-79be068bc917 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962174599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er r.2962174599 |
| Directory | /workspace/11.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.4078716045 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 64976877 ps |
| CPU time | 0.7 seconds |
| Started | Mar 14 12:23:36 PM PDT 24 |
| Finished | Mar 14 12:23:37 PM PDT 24 |
| Peak memory | 195716 kb |
| Host | smart-0d064993-7ab8-403d-90b1-cce0330325af |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078716045 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.4078716045 |
| Directory | /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2195868139 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 48352512 ps |
| CPU time | 0.62 seconds |
| Started | Mar 14 12:23:36 PM PDT 24 |
| Finished | Mar 14 12:23:37 PM PDT 24 |
| Peak memory | 197732 kb |
| Host | smart-e513c9bf-8608-443e-b16c-ffcb0a48f425 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195868139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.2195868139 |
| Directory | /workspace/12.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3715299931 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 99536063 ps |
| CPU time | 0.88 seconds |
| Started | Mar 14 12:21:19 PM PDT 24 |
| Finished | Mar 14 12:21:20 PM PDT 24 |
| Peak memory | 199192 kb |
| Host | smart-67fabbfb-0166-4bae-926a-321db546f055 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715299931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s ame_csr_outstanding.3715299931 |
| Directory | /workspace/12.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.3129731436 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 178598135 ps |
| CPU time | 2.74 seconds |
| Started | Mar 14 12:23:36 PM PDT 24 |
| Finished | Mar 14 12:23:39 PM PDT 24 |
| Peak memory | 197012 kb |
| Host | smart-0c953643-d0a2-4acb-93a3-0a4ad29a67ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129731436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.3129731436 |
| Directory | /workspace/12.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.417686385 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 295158110 ps |
| CPU time | 1.05 seconds |
| Started | Mar 14 12:24:02 PM PDT 24 |
| Finished | Mar 14 12:24:03 PM PDT 24 |
| Peak memory | 200832 kb |
| Host | smart-240f5f25-5d20-4ff2-8c65-bd894fed0ee0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417686385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_err .417686385 |
| Directory | /workspace/12.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.2926669346 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 121073411 ps |
| CPU time | 1 seconds |
| Started | Mar 14 12:23:43 PM PDT 24 |
| Finished | Mar 14 12:23:44 PM PDT 24 |
| Peak memory | 197016 kb |
| Host | smart-85f800ec-f2cd-4c35-a77e-32d459da449a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926669346 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.2926669346 |
| Directory | /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3817893898 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 25490855 ps |
| CPU time | 0.72 seconds |
| Started | Mar 14 12:23:41 PM PDT 24 |
| Finished | Mar 14 12:23:42 PM PDT 24 |
| Peak memory | 193376 kb |
| Host | smart-d11cc691-60d4-44bc-9378-9ea4ef2a5d8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817893898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.3817893898 |
| Directory | /workspace/13.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2622322377 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 35258025 ps |
| CPU time | 0.68 seconds |
| Started | Mar 14 12:22:16 PM PDT 24 |
| Finished | Mar 14 12:22:17 PM PDT 24 |
| Peak memory | 195632 kb |
| Host | smart-fad93c95-da46-4d87-8d1d-7e40a473771e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622322377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.2622322377 |
| Directory | /workspace/13.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.228258594 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 31491576 ps |
| CPU time | 0.71 seconds |
| Started | Mar 14 12:23:43 PM PDT 24 |
| Finished | Mar 14 12:23:44 PM PDT 24 |
| Peak memory | 197804 kb |
| Host | smart-3a97a5d8-96d4-4488-adc8-c9c0aa2259d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228258594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sa me_csr_outstanding.228258594 |
| Directory | /workspace/13.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.3115038675 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 82423918 ps |
| CPU time | 1.93 seconds |
| Started | Mar 14 12:23:36 PM PDT 24 |
| Finished | Mar 14 12:23:39 PM PDT 24 |
| Peak memory | 196816 kb |
| Host | smart-fbd7df33-b29a-4b32-af2b-12671fff5bc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115038675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.3115038675 |
| Directory | /workspace/13.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3039073188 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 109944697 ps |
| CPU time | 1.24 seconds |
| Started | Mar 14 12:24:02 PM PDT 24 |
| Finished | Mar 14 12:24:04 PM PDT 24 |
| Peak memory | 200468 kb |
| Host | smart-efac6f22-613e-4f8a-98cd-b6a59754e182 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039073188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er r.3039073188 |
| Directory | /workspace/13.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1635862665 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 88434532 ps |
| CPU time | 0.78 seconds |
| Started | Mar 14 12:23:43 PM PDT 24 |
| Finished | Mar 14 12:23:44 PM PDT 24 |
| Peak memory | 195708 kb |
| Host | smart-476539d2-a9df-4ed7-839c-ca09f14d06dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635862665 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.1635862665 |
| Directory | /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1577625226 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 34602771 ps |
| CPU time | 0.63 seconds |
| Started | Mar 14 12:21:57 PM PDT 24 |
| Finished | Mar 14 12:21:58 PM PDT 24 |
| Peak memory | 195744 kb |
| Host | smart-41b5f01b-2310-4cea-99cc-0cc93069436d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577625226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.1577625226 |
| Directory | /workspace/14.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.4276390596 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 71676190 ps |
| CPU time | 0.6 seconds |
| Started | Mar 14 12:23:44 PM PDT 24 |
| Finished | Mar 14 12:23:44 PM PDT 24 |
| Peak memory | 195492 kb |
| Host | smart-6741930f-758d-4b52-a2f7-5701a1d3cce6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276390596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.4276390596 |
| Directory | /workspace/14.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1158717225 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 103634380 ps |
| CPU time | 0.81 seconds |
| Started | Mar 14 12:22:07 PM PDT 24 |
| Finished | Mar 14 12:22:08 PM PDT 24 |
| Peak memory | 199248 kb |
| Host | smart-afdff77c-0969-411f-8469-465cd6b212c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158717225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s ame_csr_outstanding.1158717225 |
| Directory | /workspace/14.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.802519903 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 54597826 ps |
| CPU time | 0.97 seconds |
| Started | Mar 14 12:23:41 PM PDT 24 |
| Finished | Mar 14 12:23:43 PM PDT 24 |
| Peak memory | 193464 kb |
| Host | smart-14ff1ee9-f413-4838-9dec-7798ec02dd65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802519903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.802519903 |
| Directory | /workspace/14.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1814972177 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 127977735 ps |
| CPU time | 1.1 seconds |
| Started | Mar 14 12:22:09 PM PDT 24 |
| Finished | Mar 14 12:22:10 PM PDT 24 |
| Peak memory | 200936 kb |
| Host | smart-7270229b-04f6-4705-b50d-3e9a02409e34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814972177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er r.1814972177 |
| Directory | /workspace/14.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.527148835 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 127009810 ps |
| CPU time | 0.89 seconds |
| Started | Mar 14 12:21:19 PM PDT 24 |
| Finished | Mar 14 12:21:20 PM PDT 24 |
| Peak memory | 195736 kb |
| Host | smart-2a57a9ef-4722-4edd-b91d-1f586d1ffb2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527148835 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.527148835 |
| Directory | /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.210484430 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 49177301 ps |
| CPU time | 0.71 seconds |
| Started | Mar 14 12:23:41 PM PDT 24 |
| Finished | Mar 14 12:23:42 PM PDT 24 |
| Peak memory | 194676 kb |
| Host | smart-d2bb20ac-3be9-47aa-a0aa-3fcf25f9049b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210484430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.210484430 |
| Directory | /workspace/15.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.896956536 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 24950476 ps |
| CPU time | 0.64 seconds |
| Started | Mar 14 12:21:29 PM PDT 24 |
| Finished | Mar 14 12:21:29 PM PDT 24 |
| Peak memory | 195484 kb |
| Host | smart-7fed075e-95ba-489b-987e-d8aec4d4ff8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896956536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.896956536 |
| Directory | /workspace/15.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.443116991 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 51994330 ps |
| CPU time | 0.86 seconds |
| Started | Mar 14 12:22:21 PM PDT 24 |
| Finished | Mar 14 12:22:22 PM PDT 24 |
| Peak memory | 198956 kb |
| Host | smart-30686cb6-2797-4438-8cad-55cebcd15bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443116991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sa me_csr_outstanding.443116991 |
| Directory | /workspace/15.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.473525055 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 51780224 ps |
| CPU time | 2.44 seconds |
| Started | Mar 14 12:23:43 PM PDT 24 |
| Finished | Mar 14 12:23:46 PM PDT 24 |
| Peak memory | 196872 kb |
| Host | smart-1428e57f-ecd7-490f-9479-3da2127f7d71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473525055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.473525055 |
| Directory | /workspace/15.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.113656961 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 229661165 ps |
| CPU time | 1.48 seconds |
| Started | Mar 14 12:22:09 PM PDT 24 |
| Finished | Mar 14 12:22:11 PM PDT 24 |
| Peak memory | 201496 kb |
| Host | smart-28a299b1-b215-49a7-8053-122b3f65aac0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113656961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_err .113656961 |
| Directory | /workspace/15.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.1291670792 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 58298500 ps |
| CPU time | 1 seconds |
| Started | Mar 14 12:21:27 PM PDT 24 |
| Finished | Mar 14 12:21:28 PM PDT 24 |
| Peak memory | 195784 kb |
| Host | smart-dc886a78-7ca7-479a-974f-19da5a7db0ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291670792 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.1291670792 |
| Directory | /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1958687711 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 95096314 ps |
| CPU time | 0.66 seconds |
| Started | Mar 14 12:21:42 PM PDT 24 |
| Finished | Mar 14 12:21:43 PM PDT 24 |
| Peak memory | 195700 kb |
| Host | smart-64ec6d12-1e9b-4783-bf97-0a3b14860521 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958687711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.1958687711 |
| Directory | /workspace/16.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3596627224 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 41463352 ps |
| CPU time | 0.58 seconds |
| Started | Mar 14 12:22:07 PM PDT 24 |
| Finished | Mar 14 12:22:08 PM PDT 24 |
| Peak memory | 195924 kb |
| Host | smart-a7d6e407-913e-4d0e-9f38-ff9b7ee5d918 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596627224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.3596627224 |
| Directory | /workspace/16.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3696002258 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 39374885 ps |
| CPU time | 0.85 seconds |
| Started | Mar 14 12:23:43 PM PDT 24 |
| Finished | Mar 14 12:23:44 PM PDT 24 |
| Peak memory | 199996 kb |
| Host | smart-cde68c53-a4f1-4304-a97f-c5cd480bfd60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696002258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s ame_csr_outstanding.3696002258 |
| Directory | /workspace/16.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.4199186550 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 64348240 ps |
| CPU time | 1.34 seconds |
| Started | Mar 14 12:23:41 PM PDT 24 |
| Finished | Mar 14 12:23:43 PM PDT 24 |
| Peak memory | 194788 kb |
| Host | smart-73dd960e-9959-429d-b987-a801d650998c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199186550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.4199186550 |
| Directory | /workspace/16.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3746149288 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 113429258 ps |
| CPU time | 1.3 seconds |
| Started | Mar 14 12:21:19 PM PDT 24 |
| Finished | Mar 14 12:21:20 PM PDT 24 |
| Peak memory | 195856 kb |
| Host | smart-9cc43d30-acad-4ef5-a197-092f57f893bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746149288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er r.3746149288 |
| Directory | /workspace/16.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1099523509 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 103742880 ps |
| CPU time | 0.87 seconds |
| Started | Mar 14 12:23:47 PM PDT 24 |
| Finished | Mar 14 12:23:50 PM PDT 24 |
| Peak memory | 194084 kb |
| Host | smart-097439b8-822f-47b8-864f-a7a5639ca417 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099523509 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.1099523509 |
| Directory | /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.3372106837 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 43836928 ps |
| CPU time | 0.7 seconds |
| Started | Mar 14 12:21:34 PM PDT 24 |
| Finished | Mar 14 12:21:35 PM PDT 24 |
| Peak memory | 195696 kb |
| Host | smart-ed3ed263-1e46-41ed-b19b-1009e5d1ed64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372106837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.3372106837 |
| Directory | /workspace/17.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1223786110 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 40459267 ps |
| CPU time | 0.62 seconds |
| Started | Mar 14 12:22:20 PM PDT 24 |
| Finished | Mar 14 12:22:21 PM PDT 24 |
| Peak memory | 195664 kb |
| Host | smart-67509317-0c07-4b12-9a07-87ae936dfc1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223786110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.1223786110 |
| Directory | /workspace/17.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3898293249 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 31299125 ps |
| CPU time | 0.81 seconds |
| Started | Mar 14 12:21:42 PM PDT 24 |
| Finished | Mar 14 12:21:44 PM PDT 24 |
| Peak memory | 197852 kb |
| Host | smart-2bad3335-e7e1-4e7c-abd2-3df06a312a56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898293249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s ame_csr_outstanding.3898293249 |
| Directory | /workspace/17.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.2885385667 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 561346769 ps |
| CPU time | 1.1 seconds |
| Started | Mar 14 12:22:09 PM PDT 24 |
| Finished | Mar 14 12:22:10 PM PDT 24 |
| Peak memory | 196064 kb |
| Host | smart-c13a4bc2-4eb1-4dfa-b44d-5cae067cbfc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885385667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er r.2885385667 |
| Directory | /workspace/17.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3277410612 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 107311535 ps |
| CPU time | 1.55 seconds |
| Started | Mar 14 12:21:42 PM PDT 24 |
| Finished | Mar 14 12:21:44 PM PDT 24 |
| Peak memory | 198288 kb |
| Host | smart-8512221f-3d33-4aa3-9313-9f9c2ac6c439 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277410612 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.3277410612 |
| Directory | /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.1187199856 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 44756516 ps |
| CPU time | 0.63 seconds |
| Started | Mar 14 12:23:36 PM PDT 24 |
| Finished | Mar 14 12:23:37 PM PDT 24 |
| Peak memory | 197768 kb |
| Host | smart-eff2a853-a643-4f2c-8578-42e7267e008c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187199856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.1187199856 |
| Directory | /workspace/18.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2180986185 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 17829303 ps |
| CPU time | 0.66 seconds |
| Started | Mar 14 12:22:37 PM PDT 24 |
| Finished | Mar 14 12:22:38 PM PDT 24 |
| Peak memory | 195628 kb |
| Host | smart-67b55668-97bf-4c67-a9ab-f3aa99df7979 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180986185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.2180986185 |
| Directory | /workspace/18.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2583959196 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 39850749 ps |
| CPU time | 0.79 seconds |
| Started | Mar 14 12:21:33 PM PDT 24 |
| Finished | Mar 14 12:21:35 PM PDT 24 |
| Peak memory | 197992 kb |
| Host | smart-875c7d80-e4a2-465a-a021-9a6fef013c0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583959196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s ame_csr_outstanding.2583959196 |
| Directory | /workspace/18.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.570056993 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 112547169 ps |
| CPU time | 1.37 seconds |
| Started | Mar 14 12:23:46 PM PDT 24 |
| Finished | Mar 14 12:23:50 PM PDT 24 |
| Peak memory | 193952 kb |
| Host | smart-ef9ae9b2-f86f-4c68-a1f8-f4057b6aeeec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570056993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.570056993 |
| Directory | /workspace/18.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.2865782487 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 256300688 ps |
| CPU time | 1.61 seconds |
| Started | Mar 14 12:22:21 PM PDT 24 |
| Finished | Mar 14 12:22:22 PM PDT 24 |
| Peak memory | 201224 kb |
| Host | smart-2530e280-5d78-4f7e-9246-2a65b3e2aaec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865782487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er r.2865782487 |
| Directory | /workspace/18.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.992992857 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 48186381 ps |
| CPU time | 0.78 seconds |
| Started | Mar 14 12:23:47 PM PDT 24 |
| Finished | Mar 14 12:23:50 PM PDT 24 |
| Peak memory | 194792 kb |
| Host | smart-04941c9c-7dec-4798-a324-017925d469ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992992857 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.992992857 |
| Directory | /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.3912757305 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 42947488 ps |
| CPU time | 0.67 seconds |
| Started | Mar 14 12:23:45 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 195668 kb |
| Host | smart-98bd3d4a-fd85-4710-8f37-a431ce83895f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912757305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.3912757305 |
| Directory | /workspace/19.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.639121190 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 42179520 ps |
| CPU time | 0.6 seconds |
| Started | Mar 14 12:21:46 PM PDT 24 |
| Finished | Mar 14 12:21:47 PM PDT 24 |
| Peak memory | 195664 kb |
| Host | smart-8d19fcd4-d850-4212-88f6-0ba6cc2e5c76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639121190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.639121190 |
| Directory | /workspace/19.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2379748527 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 72205456 ps |
| CPU time | 0.76 seconds |
| Started | Mar 14 12:21:48 PM PDT 24 |
| Finished | Mar 14 12:21:49 PM PDT 24 |
| Peak memory | 197872 kb |
| Host | smart-dc252ed5-da8a-4d82-9b47-b601874e24d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379748527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s ame_csr_outstanding.2379748527 |
| Directory | /workspace/19.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.1891585965 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 160627608 ps |
| CPU time | 1.92 seconds |
| Started | Mar 14 12:22:25 PM PDT 24 |
| Finished | Mar 14 12:22:28 PM PDT 24 |
| Peak memory | 196988 kb |
| Host | smart-8472dc46-d1c5-4eaa-819c-a46d3b57c27a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891585965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.1891585965 |
| Directory | /workspace/19.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2222095567 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 26389205 ps |
| CPU time | 0.92 seconds |
| Started | Mar 14 12:23:33 PM PDT 24 |
| Finished | Mar 14 12:23:34 PM PDT 24 |
| Peak memory | 195496 kb |
| Host | smart-c9f3329a-61a1-4ed7-a8d9-99e2e43fd942 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222095567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.2 222095567 |
| Directory | /workspace/2.pwrmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.340043066 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 296522085 ps |
| CPU time | 2.32 seconds |
| Started | Mar 14 12:20:35 PM PDT 24 |
| Finished | Mar 14 12:20:38 PM PDT 24 |
| Peak memory | 195860 kb |
| Host | smart-7a6736a7-424a-4483-af14-dcefef844daa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340043066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.340043066 |
| Directory | /workspace/2.pwrmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1398280471 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 25936736 ps |
| CPU time | 0.71 seconds |
| Started | Mar 14 12:23:41 PM PDT 24 |
| Finished | Mar 14 12:23:42 PM PDT 24 |
| Peak memory | 193208 kb |
| Host | smart-b37ec514-33bd-4c9d-9258-c6d4793f6e3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398280471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.1 398280471 |
| Directory | /workspace/2.pwrmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.343087945 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 39238798 ps |
| CPU time | 1.02 seconds |
| Started | Mar 14 12:21:11 PM PDT 24 |
| Finished | Mar 14 12:21:12 PM PDT 24 |
| Peak memory | 195820 kb |
| Host | smart-cdaae6d9-9751-426c-ab47-5c5f73475b4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343087945 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.343087945 |
| Directory | /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.305892585 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 19102651 ps |
| CPU time | 0.66 seconds |
| Started | Mar 14 12:19:27 PM PDT 24 |
| Finished | Mar 14 12:19:28 PM PDT 24 |
| Peak memory | 195720 kb |
| Host | smart-d15e0dcf-aa79-4676-a7a1-74ce433c7d8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305892585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.305892585 |
| Directory | /workspace/2.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.1961753522 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 20354537 ps |
| CPU time | 0.6 seconds |
| Started | Mar 14 12:24:21 PM PDT 24 |
| Finished | Mar 14 12:24:22 PM PDT 24 |
| Peak memory | 195484 kb |
| Host | smart-837d61a5-f4b2-4127-8833-7a781070db25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961753522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.1961753522 |
| Directory | /workspace/2.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1265670911 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 25555829 ps |
| CPU time | 0.79 seconds |
| Started | Mar 14 12:20:35 PM PDT 24 |
| Finished | Mar 14 12:20:36 PM PDT 24 |
| Peak memory | 198096 kb |
| Host | smart-b1332073-77b5-43e9-bef5-08715da6ebc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265670911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa me_csr_outstanding.1265670911 |
| Directory | /workspace/2.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.2377224624 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 93306088 ps |
| CPU time | 2.19 seconds |
| Started | Mar 14 12:19:27 PM PDT 24 |
| Finished | Mar 14 12:19:30 PM PDT 24 |
| Peak memory | 196864 kb |
| Host | smart-f270e2ab-4cdc-4fd5-b0ae-7006d2b193b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377224624 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.2377224624 |
| Directory | /workspace/2.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1999808779 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 874117855 ps |
| CPU time | 1.01 seconds |
| Started | Mar 14 12:23:56 PM PDT 24 |
| Finished | Mar 14 12:23:57 PM PDT 24 |
| Peak memory | 195784 kb |
| Host | smart-252dfaea-2a35-4a7f-aaec-b3c6d4180d6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999808779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err .1999808779 |
| Directory | /workspace/2.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2182123677 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 21276203 ps |
| CPU time | 0.59 seconds |
| Started | Mar 14 12:24:18 PM PDT 24 |
| Finished | Mar 14 12:24:19 PM PDT 24 |
| Peak memory | 195456 kb |
| Host | smart-b17f7ecc-9229-4d91-98e3-53dd0c6b1692 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182123677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.2182123677 |
| Directory | /workspace/20.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.4291401864 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 44960582 ps |
| CPU time | 0.64 seconds |
| Started | Mar 14 12:23:20 PM PDT 24 |
| Finished | Mar 14 12:23:21 PM PDT 24 |
| Peak memory | 193848 kb |
| Host | smart-8d5f6a55-f4f3-4105-b19a-87287057ff13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291401864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.4291401864 |
| Directory | /workspace/21.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.3466450280 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 23238770 ps |
| CPU time | 0.65 seconds |
| Started | Mar 14 12:24:55 PM PDT 24 |
| Finished | Mar 14 12:24:57 PM PDT 24 |
| Peak memory | 193224 kb |
| Host | smart-2cfe7a75-bd12-4775-ba7d-50aa79850f18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466450280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.3466450280 |
| Directory | /workspace/22.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.1423247445 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 17946142 ps |
| CPU time | 0.62 seconds |
| Started | Mar 14 12:23:24 PM PDT 24 |
| Finished | Mar 14 12:23:25 PM PDT 24 |
| Peak memory | 194120 kb |
| Host | smart-298dc6e6-8f64-4af0-871e-8bf6a667fe7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423247445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.1423247445 |
| Directory | /workspace/23.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.548007676 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 130271402 ps |
| CPU time | 0.58 seconds |
| Started | Mar 14 12:23:46 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 195000 kb |
| Host | smart-7f13639c-86f5-4356-9a45-77b152420e83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548007676 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.548007676 |
| Directory | /workspace/24.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.2290071296 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 23781891 ps |
| CPU time | 0.68 seconds |
| Started | Mar 14 12:21:51 PM PDT 24 |
| Finished | Mar 14 12:21:52 PM PDT 24 |
| Peak memory | 195664 kb |
| Host | smart-401882a1-e86f-41fa-abc3-448f2f82e5db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290071296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.2290071296 |
| Directory | /workspace/25.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.771907904 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 30597421 ps |
| CPU time | 0.59 seconds |
| Started | Mar 14 12:23:46 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 195000 kb |
| Host | smart-3222678f-1446-479d-a7bf-e2fa5cbf5a7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771907904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.771907904 |
| Directory | /workspace/26.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.2726907050 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 20235864 ps |
| CPU time | 0.59 seconds |
| Started | Mar 14 12:23:36 PM PDT 24 |
| Finished | Mar 14 12:23:37 PM PDT 24 |
| Peak memory | 195432 kb |
| Host | smart-9e7781e1-6850-4db2-bc94-dc9cf34233eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726907050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.2726907050 |
| Directory | /workspace/27.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.2799867403 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 21955715 ps |
| CPU time | 0.66 seconds |
| Started | Mar 14 12:24:55 PM PDT 24 |
| Finished | Mar 14 12:24:57 PM PDT 24 |
| Peak memory | 193196 kb |
| Host | smart-6cd44681-c917-43c6-8bf4-12187a4ea264 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799867403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.2799867403 |
| Directory | /workspace/28.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.2806676471 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 20346334 ps |
| CPU time | 0.64 seconds |
| Started | Mar 14 12:23:45 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 193668 kb |
| Host | smart-330d7ab9-c6be-40aa-8ac6-933acdc325d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806676471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.2806676471 |
| Directory | /workspace/29.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.848010213 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 90571588 ps |
| CPU time | 1.03 seconds |
| Started | Mar 14 12:24:05 PM PDT 24 |
| Finished | Mar 14 12:24:06 PM PDT 24 |
| Peak memory | 198436 kb |
| Host | smart-67b4a9a9-1db8-4e7a-a04b-fdab2ce0bfe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848010213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.848010213 |
| Directory | /workspace/3.pwrmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2794464894 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 256937453 ps |
| CPU time | 1.84 seconds |
| Started | Mar 14 12:23:27 PM PDT 24 |
| Finished | Mar 14 12:23:29 PM PDT 24 |
| Peak memory | 195776 kb |
| Host | smart-5952b730-1d0d-48a7-97ca-b247c1e085fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794464894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.2 794464894 |
| Directory | /workspace/3.pwrmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3629446739 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 74367650 ps |
| CPU time | 0.6 seconds |
| Started | Mar 14 12:23:48 PM PDT 24 |
| Finished | Mar 14 12:23:50 PM PDT 24 |
| Peak memory | 198508 kb |
| Host | smart-7a09652b-940b-4ba8-840e-b8b1fe9681e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629446739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.3 629446739 |
| Directory | /workspace/3.pwrmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.739518798 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 41851508 ps |
| CPU time | 0.63 seconds |
| Started | Mar 14 12:22:10 PM PDT 24 |
| Finished | Mar 14 12:22:10 PM PDT 24 |
| Peak memory | 195708 kb |
| Host | smart-fa6c3f19-2e33-4ac5-8666-cd93e5f5e83c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739518798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.739518798 |
| Directory | /workspace/3.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.4216137038 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 30316405 ps |
| CPU time | 0.64 seconds |
| Started | Mar 14 12:20:18 PM PDT 24 |
| Finished | Mar 14 12:20:19 PM PDT 24 |
| Peak memory | 195584 kb |
| Host | smart-dfff7948-de97-4ae1-9d75-031576b30ca9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216137038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.4216137038 |
| Directory | /workspace/3.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.2535013885 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 58159324 ps |
| CPU time | 0.8 seconds |
| Started | Mar 14 12:19:10 PM PDT 24 |
| Finished | Mar 14 12:19:11 PM PDT 24 |
| Peak memory | 199188 kb |
| Host | smart-642ca0b8-6ecf-4e22-aed5-e54d57460770 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535013885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa me_csr_outstanding.2535013885 |
| Directory | /workspace/3.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.648506898 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 891135846 ps |
| CPU time | 1.69 seconds |
| Started | Mar 14 12:21:53 PM PDT 24 |
| Finished | Mar 14 12:21:54 PM PDT 24 |
| Peak memory | 197252 kb |
| Host | smart-1ae866be-dc54-4644-b64f-c193fce4dace |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648506898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.648506898 |
| Directory | /workspace/3.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3416560298 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 153135655 ps |
| CPU time | 1.2 seconds |
| Started | Mar 14 12:22:00 PM PDT 24 |
| Finished | Mar 14 12:22:01 PM PDT 24 |
| Peak memory | 196028 kb |
| Host | smart-4981e398-2393-4355-b0ce-1e50adbe903c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416560298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err .3416560298 |
| Directory | /workspace/3.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.4258763784 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 19378711 ps |
| CPU time | 0.59 seconds |
| Started | Mar 14 12:23:36 PM PDT 24 |
| Finished | Mar 14 12:23:37 PM PDT 24 |
| Peak memory | 195432 kb |
| Host | smart-af116547-4387-414e-8484-11148e360616 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258763784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.4258763784 |
| Directory | /workspace/30.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2800230386 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 63237973 ps |
| CPU time | 0.65 seconds |
| Started | Mar 14 12:23:37 PM PDT 24 |
| Finished | Mar 14 12:23:39 PM PDT 24 |
| Peak memory | 193792 kb |
| Host | smart-60d22f1d-39cf-4923-8b21-537190199e24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800230386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.2800230386 |
| Directory | /workspace/31.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3844211666 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 19795117 ps |
| CPU time | 0.6 seconds |
| Started | Mar 14 12:23:39 PM PDT 24 |
| Finished | Mar 14 12:23:40 PM PDT 24 |
| Peak memory | 195216 kb |
| Host | smart-389c8dc4-bacc-47a2-96e2-e7b02ceeb487 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844211666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.3844211666 |
| Directory | /workspace/32.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.2892059132 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 24843176 ps |
| CPU time | 0.62 seconds |
| Started | Mar 14 12:21:58 PM PDT 24 |
| Finished | Mar 14 12:21:58 PM PDT 24 |
| Peak memory | 195560 kb |
| Host | smart-f2a76bf9-ddc3-40c8-b65d-179705e9f358 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892059132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.2892059132 |
| Directory | /workspace/33.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2238084873 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 37214778 ps |
| CPU time | 0.58 seconds |
| Started | Mar 14 12:23:38 PM PDT 24 |
| Finished | Mar 14 12:23:39 PM PDT 24 |
| Peak memory | 194448 kb |
| Host | smart-0cfdcded-3942-4b4f-bb2f-9f0d2297c50b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238084873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.2238084873 |
| Directory | /workspace/34.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.61469599 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 123612486 ps |
| CPU time | 0.61 seconds |
| Started | Mar 14 12:23:38 PM PDT 24 |
| Finished | Mar 14 12:23:39 PM PDT 24 |
| Peak memory | 194252 kb |
| Host | smart-d88a985d-9cfe-4ee3-80a9-dc2c88ba894c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61469599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.61469599 |
| Directory | /workspace/35.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3481413976 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 15963887 ps |
| CPU time | 0.68 seconds |
| Started | Mar 14 12:23:38 PM PDT 24 |
| Finished | Mar 14 12:23:39 PM PDT 24 |
| Peak memory | 194084 kb |
| Host | smart-12251c42-b7bc-4172-a13d-ebcdcedc8ea0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481413976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.3481413976 |
| Directory | /workspace/36.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.1623415569 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 35222300 ps |
| CPU time | 0.61 seconds |
| Started | Mar 14 12:23:38 PM PDT 24 |
| Finished | Mar 14 12:23:39 PM PDT 24 |
| Peak memory | 194008 kb |
| Host | smart-64e68f8e-024e-465a-a389-ceca6bce1633 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623415569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.1623415569 |
| Directory | /workspace/37.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.3179857966 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 16580347 ps |
| CPU time | 0.61 seconds |
| Started | Mar 14 12:24:58 PM PDT 24 |
| Finished | Mar 14 12:24:59 PM PDT 24 |
| Peak memory | 195400 kb |
| Host | smart-bbde0e2f-bc12-496a-a3b6-0c5ba82c845e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179857966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.3179857966 |
| Directory | /workspace/38.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.1416499694 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 28252073 ps |
| CPU time | 0.63 seconds |
| Started | Mar 14 12:21:58 PM PDT 24 |
| Finished | Mar 14 12:21:58 PM PDT 24 |
| Peak memory | 195560 kb |
| Host | smart-f71e87a9-74d9-44bb-890f-099e5468af1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416499694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.1416499694 |
| Directory | /workspace/39.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.2555932447 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 146022310 ps |
| CPU time | 1 seconds |
| Started | Mar 14 12:24:29 PM PDT 24 |
| Finished | Mar 14 12:24:31 PM PDT 24 |
| Peak memory | 195536 kb |
| Host | smart-cfdd862e-89a8-44e0-b20b-80c0dd6e8b03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555932447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.2 555932447 |
| Directory | /workspace/4.pwrmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.174576462 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1515561346 ps |
| CPU time | 3.33 seconds |
| Started | Mar 14 12:24:29 PM PDT 24 |
| Finished | Mar 14 12:24:33 PM PDT 24 |
| Peak memory | 195516 kb |
| Host | smart-02edb1d8-6a7c-4c60-b7cd-aa58eec6d853 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174576462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.174576462 |
| Directory | /workspace/4.pwrmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.736143438 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 23777601 ps |
| CPU time | 0.7 seconds |
| Started | Mar 14 12:23:47 PM PDT 24 |
| Finished | Mar 14 12:23:49 PM PDT 24 |
| Peak memory | 197048 kb |
| Host | smart-b1f13530-e36f-469e-901b-a02031f00f57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736143438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.736143438 |
| Directory | /workspace/4.pwrmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.4216155078 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 58067798 ps |
| CPU time | 0.93 seconds |
| Started | Mar 14 12:20:53 PM PDT 24 |
| Finished | Mar 14 12:20:54 PM PDT 24 |
| Peak memory | 195808 kb |
| Host | smart-5d41bf25-4cf6-4abc-a393-8409f38340f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216155078 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.4216155078 |
| Directory | /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.1975045572 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 16822566 ps |
| CPU time | 0.69 seconds |
| Started | Mar 14 12:21:14 PM PDT 24 |
| Finished | Mar 14 12:21:15 PM PDT 24 |
| Peak memory | 197852 kb |
| Host | smart-34a58834-4238-40a1-a458-5394bdde5244 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975045572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.1975045572 |
| Directory | /workspace/4.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.2761959734 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 30713226 ps |
| CPU time | 0.58 seconds |
| Started | Mar 14 12:24:17 PM PDT 24 |
| Finished | Mar 14 12:24:18 PM PDT 24 |
| Peak memory | 194984 kb |
| Host | smart-e81e0afb-f16d-4825-b5db-0fcbdd9551f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761959734 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.2761959734 |
| Directory | /workspace/4.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.4072073666 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 24515706 ps |
| CPU time | 0.85 seconds |
| Started | Mar 14 12:22:26 PM PDT 24 |
| Finished | Mar 14 12:22:27 PM PDT 24 |
| Peak memory | 198936 kb |
| Host | smart-6de61c90-b254-41f4-b794-68ab7d57dfd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072073666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa me_csr_outstanding.4072073666 |
| Directory | /workspace/4.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.1297523168 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 262182286 ps |
| CPU time | 2.73 seconds |
| Started | Mar 14 12:21:51 PM PDT 24 |
| Finished | Mar 14 12:21:54 PM PDT 24 |
| Peak memory | 198040 kb |
| Host | smart-e2a57127-c967-481c-9cf7-542b4bcb26d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297523168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.1297523168 |
| Directory | /workspace/4.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.3214623617 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 147723158 ps |
| CPU time | 1.1 seconds |
| Started | Mar 14 12:23:31 PM PDT 24 |
| Finished | Mar 14 12:23:33 PM PDT 24 |
| Peak memory | 199396 kb |
| Host | smart-cf885d2b-3e91-4b2f-b708-9ba30f8b9dd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214623617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err .3214623617 |
| Directory | /workspace/4.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.2633248325 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 17314350 ps |
| CPU time | 0.64 seconds |
| Started | Mar 14 12:24:42 PM PDT 24 |
| Finished | Mar 14 12:24:43 PM PDT 24 |
| Peak memory | 194412 kb |
| Host | smart-8111df64-0c46-4423-990c-a65d1e133486 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633248325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.2633248325 |
| Directory | /workspace/40.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.3391176078 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 45397658 ps |
| CPU time | 0.64 seconds |
| Started | Mar 14 12:22:05 PM PDT 24 |
| Finished | Mar 14 12:22:06 PM PDT 24 |
| Peak memory | 195668 kb |
| Host | smart-ece14877-721c-4fa8-bd4c-c1971999f872 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391176078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.3391176078 |
| Directory | /workspace/41.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.4148271181 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 27372341 ps |
| CPU time | 0.64 seconds |
| Started | Mar 14 12:22:04 PM PDT 24 |
| Finished | Mar 14 12:22:05 PM PDT 24 |
| Peak memory | 195664 kb |
| Host | smart-172eeb37-d4d2-4924-ae9f-e6e0a1ff20d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148271181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.4148271181 |
| Directory | /workspace/42.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.797683434 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 22535145 ps |
| CPU time | 0.65 seconds |
| Started | Mar 14 12:22:04 PM PDT 24 |
| Finished | Mar 14 12:22:05 PM PDT 24 |
| Peak memory | 195668 kb |
| Host | smart-cb93325a-2c0f-4ef2-adcb-a56379afa305 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797683434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.797683434 |
| Directory | /workspace/43.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.3497062438 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 21093677 ps |
| CPU time | 0.62 seconds |
| Started | Mar 14 12:23:38 PM PDT 24 |
| Finished | Mar 14 12:23:39 PM PDT 24 |
| Peak memory | 195184 kb |
| Host | smart-4983c78e-1480-44bf-b74e-ff965b863106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497062438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.3497062438 |
| Directory | /workspace/44.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.1794493379 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 128568525 ps |
| CPU time | 0.6 seconds |
| Started | Mar 14 12:23:46 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 195004 kb |
| Host | smart-a0ffbb79-b5b9-447f-b418-e8fef3654e05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794493379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.1794493379 |
| Directory | /workspace/45.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3908410872 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 35093332 ps |
| CPU time | 0.6 seconds |
| Started | Mar 14 12:24:43 PM PDT 24 |
| Finished | Mar 14 12:24:44 PM PDT 24 |
| Peak memory | 195152 kb |
| Host | smart-db84520e-b63f-49d1-8240-4dc8e0696ed8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908410872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.3908410872 |
| Directory | /workspace/46.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.4167769858 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 24904416 ps |
| CPU time | 0.65 seconds |
| Started | Mar 14 12:23:37 PM PDT 24 |
| Finished | Mar 14 12:23:39 PM PDT 24 |
| Peak memory | 194016 kb |
| Host | smart-2d3b26ff-80c9-49a8-826b-927ef0c6bb4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167769858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.4167769858 |
| Directory | /workspace/47.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.3129964515 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 18097096 ps |
| CPU time | 0.59 seconds |
| Started | Mar 14 12:21:57 PM PDT 24 |
| Finished | Mar 14 12:21:58 PM PDT 24 |
| Peak memory | 195664 kb |
| Host | smart-df507400-dd0b-4bf4-a96f-098067434857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129964515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.3129964515 |
| Directory | /workspace/48.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1796130021 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 54442887 ps |
| CPU time | 0.65 seconds |
| Started | Mar 14 12:22:11 PM PDT 24 |
| Finished | Mar 14 12:22:12 PM PDT 24 |
| Peak memory | 195668 kb |
| Host | smart-0ac9d2cd-2302-4d0d-bf83-1b7b11f189b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796130021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.1796130021 |
| Directory | /workspace/49.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3545132775 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 48368175 ps |
| CPU time | 1.04 seconds |
| Started | Mar 14 12:21:55 PM PDT 24 |
| Finished | Mar 14 12:21:57 PM PDT 24 |
| Peak memory | 195820 kb |
| Host | smart-f18f383e-a205-4b6e-8258-5261c11c56c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545132775 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.3545132775 |
| Directory | /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3575030944 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 41369345 ps |
| CPU time | 0.69 seconds |
| Started | Mar 14 12:23:45 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 195932 kb |
| Host | smart-4c4ab86d-a6c4-41a4-bbf5-d6c6ae3ff25d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575030944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.3575030944 |
| Directory | /workspace/5.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.3527408554 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 17636061 ps |
| CPU time | 0.6 seconds |
| Started | Mar 14 12:24:29 PM PDT 24 |
| Finished | Mar 14 12:24:30 PM PDT 24 |
| Peak memory | 195284 kb |
| Host | smart-91cc461e-b5ee-4db0-ae2a-197356086637 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527408554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.3527408554 |
| Directory | /workspace/5.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1855160661 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 125754496 ps |
| CPU time | 0.82 seconds |
| Started | Mar 14 12:23:46 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 198696 kb |
| Host | smart-10650861-70cf-430f-a20c-d4cbf048200c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855160661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa me_csr_outstanding.1855160661 |
| Directory | /workspace/5.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2035083519 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 112258691 ps |
| CPU time | 1.45 seconds |
| Started | Mar 14 12:21:26 PM PDT 24 |
| Finished | Mar 14 12:21:28 PM PDT 24 |
| Peak memory | 196140 kb |
| Host | smart-5b722629-ed12-41aa-954d-7d06bc6f66af |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035083519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.2035083519 |
| Directory | /workspace/5.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.1782702356 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 200178156 ps |
| CPU time | 1.1 seconds |
| Started | Mar 14 12:24:14 PM PDT 24 |
| Finished | Mar 14 12:24:16 PM PDT 24 |
| Peak memory | 199512 kb |
| Host | smart-ecd8a459-053b-4ee8-aa6c-7bbcdf0664e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782702356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err .1782702356 |
| Directory | /workspace/5.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.421011760 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 41879215 ps |
| CPU time | 1.1 seconds |
| Started | Mar 14 12:23:45 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 194844 kb |
| Host | smart-f5fefe95-4810-4942-8b9f-126c489da912 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421011760 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.421011760 |
| Directory | /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1204669373 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 18951961 ps |
| CPU time | 0.67 seconds |
| Started | Mar 14 12:21:11 PM PDT 24 |
| Finished | Mar 14 12:21:12 PM PDT 24 |
| Peak memory | 197932 kb |
| Host | smart-ed1b2e7a-d1aa-4522-bd10-a7c1203e79a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204669373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.1204669373 |
| Directory | /workspace/6.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.136753940 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 55345209 ps |
| CPU time | 0.6 seconds |
| Started | Mar 14 12:24:01 PM PDT 24 |
| Finished | Mar 14 12:24:02 PM PDT 24 |
| Peak memory | 195468 kb |
| Host | smart-d5de35df-ec17-4448-bced-f8f90ebc29bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136753940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.136753940 |
| Directory | /workspace/6.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2242156120 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 81083433 ps |
| CPU time | 0.83 seconds |
| Started | Mar 14 12:24:02 PM PDT 24 |
| Finished | Mar 14 12:24:03 PM PDT 24 |
| Peak memory | 200368 kb |
| Host | smart-9e29cf5d-07ba-49c3-ac7e-eeef724caf72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242156120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa me_csr_outstanding.2242156120 |
| Directory | /workspace/6.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.1820134030 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 694586944 ps |
| CPU time | 1.98 seconds |
| Started | Mar 14 12:23:45 PM PDT 24 |
| Finished | Mar 14 12:23:48 PM PDT 24 |
| Peak memory | 196632 kb |
| Host | smart-4669250a-63de-458d-830a-21aec5fd32f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820134030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.1820134030 |
| Directory | /workspace/6.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.688336465 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 200025213 ps |
| CPU time | 1.6 seconds |
| Started | Mar 14 12:20:54 PM PDT 24 |
| Finished | Mar 14 12:20:56 PM PDT 24 |
| Peak memory | 201128 kb |
| Host | smart-42a533e9-a98d-4dc1-a9ad-003812c71bd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688336465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err. 688336465 |
| Directory | /workspace/6.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2711876304 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 51210683 ps |
| CPU time | 1.17 seconds |
| Started | Mar 14 12:21:46 PM PDT 24 |
| Finished | Mar 14 12:21:47 PM PDT 24 |
| Peak memory | 196020 kb |
| Host | smart-b05fa2b9-6722-45f9-85f1-428f80d351fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711876304 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.2711876304 |
| Directory | /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.100860692 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 29537709 ps |
| CPU time | 0.67 seconds |
| Started | Mar 14 12:24:02 PM PDT 24 |
| Finished | Mar 14 12:24:03 PM PDT 24 |
| Peak memory | 197756 kb |
| Host | smart-4bfb870d-afd0-4113-a71e-9e5dd58ae54c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100860692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.100860692 |
| Directory | /workspace/7.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.652540291 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 18306427 ps |
| CPU time | 0.68 seconds |
| Started | Mar 14 12:20:57 PM PDT 24 |
| Finished | Mar 14 12:20:58 PM PDT 24 |
| Peak memory | 195632 kb |
| Host | smart-a60a047b-8160-4f7a-955a-c9275a045672 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652540291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.652540291 |
| Directory | /workspace/7.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1643511120 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 31412807 ps |
| CPU time | 0.88 seconds |
| Started | Mar 14 12:24:02 PM PDT 24 |
| Finished | Mar 14 12:24:03 PM PDT 24 |
| Peak memory | 195532 kb |
| Host | smart-ab1d7a34-9e26-40a6-8d03-fd4bdcf6963f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643511120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa me_csr_outstanding.1643511120 |
| Directory | /workspace/7.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1803315641 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 56400572 ps |
| CPU time | 1.35 seconds |
| Started | Mar 14 12:24:03 PM PDT 24 |
| Finished | Mar 14 12:24:04 PM PDT 24 |
| Peak memory | 196060 kb |
| Host | smart-626d8f53-0d50-48d8-a5ee-8bb7a582c263 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803315641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.1803315641 |
| Directory | /workspace/7.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2568199800 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 58038729 ps |
| CPU time | 0.94 seconds |
| Started | Mar 14 12:23:46 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 200488 kb |
| Host | smart-b9a73cfc-b33c-4752-81e3-9ee39fa9081e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568199800 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.2568199800 |
| Directory | /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.764260430 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 29175350 ps |
| CPU time | 0.69 seconds |
| Started | Mar 14 12:22:04 PM PDT 24 |
| Finished | Mar 14 12:22:05 PM PDT 24 |
| Peak memory | 197896 kb |
| Host | smart-02867418-dd6e-4526-a27d-327acefa62b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764260430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.764260430 |
| Directory | /workspace/8.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.795247692 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 26559566 ps |
| CPU time | 0.61 seconds |
| Started | Mar 14 12:24:03 PM PDT 24 |
| Finished | Mar 14 12:24:03 PM PDT 24 |
| Peak memory | 195468 kb |
| Host | smart-e3480e96-ebd5-4ec5-b486-1cc0fa02510a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795247692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.795247692 |
| Directory | /workspace/8.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.983048545 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 41824588 ps |
| CPU time | 0.8 seconds |
| Started | Mar 14 12:23:45 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 198740 kb |
| Host | smart-e7a708d5-35f4-4df0-994a-3896d0efebba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983048545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sam e_csr_outstanding.983048545 |
| Directory | /workspace/8.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1133146580 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 161754672 ps |
| CPU time | 2.41 seconds |
| Started | Mar 14 12:23:46 PM PDT 24 |
| Finished | Mar 14 12:23:49 PM PDT 24 |
| Peak memory | 196508 kb |
| Host | smart-baebf2dc-8833-4173-95f3-19b88b496f64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133146580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.1133146580 |
| Directory | /workspace/8.pwrmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.965456530 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 239863968 ps |
| CPU time | 1 seconds |
| Started | Mar 14 12:23:46 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 195324 kb |
| Host | smart-7e09654b-2826-41d0-80b8-cccdb3942a94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965456530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err. 965456530 |
| Directory | /workspace/8.pwrmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3196196114 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 36404101 ps |
| CPU time | 0.91 seconds |
| Started | Mar 14 12:23:45 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 194168 kb |
| Host | smart-4df2b0c8-8f15-46e3-bf97-6c3309a88f53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196196114 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.3196196114 |
| Directory | /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.1024489803 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 42742837 ps |
| CPU time | 0.69 seconds |
| Started | Mar 14 12:23:44 PM PDT 24 |
| Finished | Mar 14 12:23:45 PM PDT 24 |
| Peak memory | 196944 kb |
| Host | smart-e37cbccf-dcf7-4a9f-b601-a1d46959b485 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024489803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.1024489803 |
| Directory | /workspace/9.pwrmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2919530136 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 20071770 ps |
| CPU time | 0.6 seconds |
| Started | Mar 14 12:24:03 PM PDT 24 |
| Finished | Mar 14 12:24:03 PM PDT 24 |
| Peak memory | 195260 kb |
| Host | smart-52d2dc5f-1488-4202-9da0-a453b5bb8e2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919530136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.2919530136 |
| Directory | /workspace/9.pwrmgr_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.3960797068 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 23278031 ps |
| CPU time | 0.74 seconds |
| Started | Mar 14 12:23:46 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 198328 kb |
| Host | smart-c2bb05ab-6e56-4b83-9991-7021b6aa6180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960797068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa me_csr_outstanding.3960797068 |
| Directory | /workspace/9.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.331839327 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 56612507 ps |
| CPU time | 1.42 seconds |
| Started | Mar 14 12:23:44 PM PDT 24 |
| Finished | Mar 14 12:23:47 PM PDT 24 |
| Peak memory | 195084 kb |
| Host | smart-2e0c912c-599b-4479-9210-f6c36fdd2537 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331839327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.331839327 |
| Directory | /workspace/9.pwrmgr_tl_errors/latest |
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