| | | | | | | | | | | |
|
alert_esc_agent_pkg::esc_handshake_complete_cg |
0 |
3 |
0.00 |
0.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg |
0 |
2 |
0.00 |
0.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
pwrmgr_env_pkg::pwrmgr_env_cov::control_cg |
0 |
76 |
0.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
pwrmgr_env_pkg::pwrmgr_env_cov::esc_reset_cg |
0 |
7 |
0.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg |
0 |
12 |
0.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg |
0 |
12 |
0.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
pwrmgr_env_pkg::pwrmgr_env_cov::main_power_reset_cg |
0 |
7 |
0.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
pwrmgr_env_pkg::pwrmgr_env_cov::reset_wakeup_distance_cg |
0 |
9 |
0.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
pwrmgr_env_pkg::pwrmgr_env_cov::rstmgr_sw_reset_cg |
0 |
2 |
0.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
pwrmgr_env_pkg::pwrmgr_wakeup_ctrl_cg_wrap::wakeup_ctrl_cg |
0 |
14 |
0.00 |
0.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
dv_base_reg_pkg::mubi_cov#(4,32'sb00000000000000000000000000000101,32'sb00000000000000000000000000001010)::mubi_cg |
1 |
6 |
16.67 |
16.67 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg |
5 |
24 |
20.83 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
pwrmgr_env_pkg::pwrmgr_wakeup_intr_cg_wrap::wakeup_intr_cg |
5 |
16 |
31.25 |
31.25 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
dv_base_reg_pkg::mubi_cov#(4,32'sh00000006,32'sh00000009)::mubi_cg |
2 |
6 |
33.33 |
16.67 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
tl_agent_pkg::pending_req_on_rst_cg |
1 |
2 |
50.00 |
50.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg |
12 |
15 |
80.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg |
13 |
14 |
92.86 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
alert_esc_agent_pkg::alert_handshake_complete_cg |
3 |
3 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=0} |
9 |
9 |
100.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=0} |
9 |
9 |
100.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0} |
13 |
13 |
100.00 |
|
1 |
100 |
1 |
0 |
64 |
64 |
|
|
dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg |
2 |
2 |
100.00 |
75.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg |
4 |
4 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=1} |
1 |
1 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
|
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128} |
137 |
137 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|