Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::main_power_reset_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::main_power_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

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Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::main_power_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	4	0	0.00
Crosses	3	3	0	0.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::main_power_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
main_power_reset_cp	2	2	0	0.00	100	1	1	2
sleep_cp	2	2	0	0.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::main_power_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
reset_cross	3	3	0	0.00	100	1	1	0

Summary for Variable main_power_reset_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for main_power_reset_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

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Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

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Summary for Cross reset_cross

Samples crossed: main_power_reset_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	3	3	0	0.00	3
Automatically Generated Cross Bins	3	3	0	0.00	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for reset_cross

Element holes

main_power_reset_cp	sleep_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	--	--	2

Uncovered bins

main_power_reset_cp	sleep_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	0	1	1

User Defined Cross Bins for reset_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal	0	Illegal