Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	488114	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

188007

1

T1

1

T2

209

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	358244	1			T1	1		T2	406		T3	1
values[0x0]	158379	1			T2	234		T4	5		T5	65
values[0x1]	159498	1			T2	218		T4	5		T5	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	386296	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

289825

1

T1

1

T2

353

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2172	1			T2	6		T5	2		T6	4
valid_sources[0x01]	2220	1			T2	5		T5	2		T6	2
valid_sources[0x02]	2098	1			T2	8		T5	1		T6	7
valid_sources[0x03]	2255	1			T2	3		T4	2		T6	1
valid_sources[0x04]	2819	1			T2	3		T5	4		T6	2
valid_sources[0x05]	2217	1			T2	7		T6	6		T7	2
valid_sources[0x06]	2173	1			T2	1		T5	1		T6	3
valid_sources[0x07]	3979	1			T2	7		T5	1		T6	8
valid_sources[0x08]	2489	1			T2	16		T6	5		T7	13
valid_sources[0x09]	2331	1			T2	3		T6	3		T8	18
valid_sources[0x0a]	2368	1			T2	1		T6	3		T8	12
valid_sources[0x0b]	2462	1			T2	1		T6	4		T8	17
valid_sources[0x0c]	2346	1			T2	4		T6	5		T8	14
valid_sources[0x0d]	1907	1			T2	5		T5	1		T6	4
valid_sources[0x0e]	2793	1			T2	6		T6	3		T8	7
valid_sources[0x0f]	2989	1			T2	4		T5	1		T6	2
valid_sources[0x10]	2228	1			T2	1		T6	6		T7	1
valid_sources[0x11]	1906	1			T2	4		T5	3		T6	1
valid_sources[0x12]	1954	1			T2	5		T5	1		T6	1
valid_sources[0x13]	4863	1			T5	1		T8	17		T39	1
valid_sources[0x14]	4477	1			T5	3		T6	4		T8	11
valid_sources[0x15]	2136	1			T4	1		T6	3		T8	7
valid_sources[0x16]	3185	1			T5	1		T6	4		T8	15
valid_sources[0x17]	1998	1			T6	2		T7	1		T8	7
valid_sources[0x18]	4038	1			T2	1		T6	2		T8	25
valid_sources[0x19]	3333	1			T6	3		T8	14		T14	1
valid_sources[0x1a]	3205	1			T2	6		T6	3		T7	1
valid_sources[0x1b]	1904	1			T2	2		T4	1		T6	4
valid_sources[0x1c]	2239	1			T2	5		T5	3		T6	1
valid_sources[0x1d]	2128	1			T2	6		T4	2		T5	1
valid_sources[0x1e]	2560	1			T2	1		T6	1		T8	16
valid_sources[0x1f]	2428	1			T2	5		T4	1		T5	1
valid_sources[0x20]	3590	1			T2	7		T5	2		T6	4
valid_sources[0x21]	2122	1			T6	1		T7	1		T8	9
valid_sources[0x22]	2623	1			T6	2		T7	1		T8	16
valid_sources[0x23]	2031	1			T4	1		T5	2		T6	3
valid_sources[0x24]	2105	1			T2	1		T5	1		T6	1
valid_sources[0x25]	2140	1			T5	2		T6	7		T8	28
valid_sources[0x26]	3609	1			T2	5		T5	3		T6	2
valid_sources[0x27]	2193	1			T1	1		T2	1		T5	1
valid_sources[0x28]	1907	1			T2	9		T6	2		T8	11
valid_sources[0x29]	2498	1			T5	1		T6	5		T8	21
valid_sources[0x2a]	2246	1			T2	2		T3	1		T5	1
valid_sources[0x2b]	2324	1			T5	1		T6	2		T8	10
valid_sources[0x2c]	1869	1			T2	1		T6	1		T7	1
valid_sources[0x2d]	2171	1			T2	3		T5	6		T6	1
valid_sources[0x2e]	2058	1			T2	8		T6	5		T7	8
valid_sources[0x2f]	2371	1			T2	4		T4	1		T5	1
valid_sources[0x30]	2057	1			T2	3		T5	4		T6	5
valid_sources[0x31]	2149	1			T2	1		T6	3		T8	13
valid_sources[0x32]	2219	1			T2	9		T5	1		T8	26
valid_sources[0x33]	2810	1			T2	7		T4	1		T5	1
valid_sources[0x34]	2187	1			T2	1		T5	2		T8	15
valid_sources[0x35]	2039	1			T2	2		T5	1		T6	5
valid_sources[0x36]	1822	1			T2	1		T5	2		T6	1
valid_sources[0x37]	2440	1			T2	1		T5	2		T6	6
valid_sources[0x38]	2235	1			T5	2		T6	3		T8	12
valid_sources[0x39]	3505	1			T6	5		T8	14		T37	2
valid_sources[0x3a]	3530	1			T2	1		T6	6		T8	7
valid_sources[0x3b]	1995	1			T2	3		T5	2		T6	2
valid_sources[0x3c]	3834	1			T2	1		T7	4		T8	11
valid_sources[0x3d]	4482	1			T2	2		T8	16		T14	1
valid_sources[0x3e]	2843	1			T6	3		T8	24		T39	1
valid_sources[0x3f]	2439	1			T6	1		T7	2		T8	9
valid_sources[0x40]	2838	1			T2	3		T5	1		T6	2
valid_sources[0x41]	1954	1			T2	3		T5	2		T6	5
valid_sources[0x42]	2198	1			T2	8		T6	5		T8	21
valid_sources[0x43]	2125	1			T2	1		T4	1		T6	1
valid_sources[0x44]	2588	1			T2	3		T5	3		T6	2
valid_sources[0x45]	5732	1			T2	3		T4	1		T5	2
valid_sources[0x46]	1951	1			T2	4		T5	1		T6	2
valid_sources[0x47]	2017	1			T5	3		T6	3		T7	1
valid_sources[0x48]	2591	1			T2	2		T6	5		T8	13
valid_sources[0x49]	2088	1			T2	1		T5	4		T6	3
valid_sources[0x4a]	3130	1			T2	5		T4	1		T6	10
valid_sources[0x4b]	2366	1			T2	4		T5	3		T6	6
valid_sources[0x4c]	3056	1			T2	3		T8	11		T14	1
valid_sources[0x4d]	2119	1			T2	2		T6	3		T7	1
valid_sources[0x4e]	2020	1			T2	4		T5	1		T6	5
valid_sources[0x4f]	3249	1			T2	2		T6	5		T8	25
valid_sources[0x50]	2455	1			T2	4		T6	2		T8	18
valid_sources[0x51]	3630	1			T2	1		T4	1		T5	3
valid_sources[0x52]	2491	1			T2	5		T5	1		T6	3
valid_sources[0x53]	2159	1			T2	3		T5	1		T6	4
valid_sources[0x54]	2029	1			T2	13		T6	3		T7	1
valid_sources[0x55]	2391	1			T2	1		T6	5		T8	12
valid_sources[0x56]	3314	1			T2	8		T4	1		T6	6
valid_sources[0x57]	3375	1			T2	1		T8	10		T15	26
valid_sources[0x58]	2355	1			T2	2		T5	2		T6	5
valid_sources[0x59]	2440	1			T2	2		T5	6		T6	1
valid_sources[0x5a]	3033	1			T2	6		T5	2		T8	13
valid_sources[0x5b]	2594	1			T2	3		T6	3		T8	10
valid_sources[0x5c]	2408	1			T2	6		T6	6		T8	15
valid_sources[0x5d]	2454	1			T4	2		T6	10		T8	16
valid_sources[0x5e]	2083	1			T2	4		T6	3		T7	1
valid_sources[0x5f]	2135	1			T6	2		T7	2		T8	15
valid_sources[0x60]	3683	1			T2	3		T6	1		T8	10
valid_sources[0x61]	2775	1			T2	3		T6	3		T8	16
valid_sources[0x62]	2053	1			T2	4		T5	2		T6	7
valid_sources[0x63]	2209	1			T2	1		T6	2		T7	5
valid_sources[0x64]	2978	1			T2	3		T6	5		T8	13
valid_sources[0x65]	1896	1			T2	1		T5	2		T6	6
valid_sources[0x66]	2354	1			T2	3		T6	4		T8	16
valid_sources[0x67]	2126	1			T5	1		T6	6		T7	4
valid_sources[0x68]	1931	1			T5	3		T6	6		T8	14
valid_sources[0x69]	2020	1			T2	3		T6	6		T8	10
valid_sources[0x6a]	2739	1			T2	1		T5	1		T6	7
valid_sources[0x6b]	2240	1			T2	7		T5	2		T6	3
valid_sources[0x6c]	3228	1			T2	1		T6	1		T8	26
valid_sources[0x6d]	2587	1			T2	5		T6	6		T8	13
valid_sources[0x6e]	3375	1			T2	3		T6	5		T8	27
valid_sources[0x6f]	3347	1			T2	2		T6	4		T8	4
valid_sources[0x70]	2336	1			T2	3		T8	25		T14	1
valid_sources[0x71]	1923	1			T2	1		T6	1		T8	10
valid_sources[0x72]	2119	1			T2	1		T5	3		T6	3
valid_sources[0x73]	2265	1			T2	7		T5	1		T6	7
valid_sources[0x74]	7414	1			T2	3		T5	1		T6	1
valid_sources[0x75]	2373	1			T2	2		T6	1		T8	18
valid_sources[0x76]	1881	1			T2	3		T6	2		T8	3
valid_sources[0x77]	1985	1			T2	6		T6	2		T8	10
valid_sources[0x78]	2392	1			T4	2		T6	5		T8	11
valid_sources[0x79]	1951	1			T2	1		T4	2		T5	1
valid_sources[0x7a]	2663	1			T2	5		T5	1		T6	1
valid_sources[0x7b]	2854	1			T2	5		T5	1		T6	3
valid_sources[0x7c]	2115	1			T2	1		T5	1		T8	14
valid_sources[0x7d]	4024	1			T2	15		T5	1		T6	3
valid_sources[0x7e]	2086	1			T2	4		T6	1		T8	14
valid_sources[0x7f]	2959	1			T2	3		T6	4		T7	4
valid_sources[0x80]	2076	1			T2	8		T5	1		T6	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

97137

1

T1

1

T2

78

T3

1

values[0x0]

all_enables

biggest_size

58745

1

T2

88

T4

1

T5

17

values[0x1]

all_enables

biggest_size

32125

1

T2

43

T5

9

T6

43