SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34985 | 1 | T2 | 318 | T6 | 384 | T23 | 299 | ||||
others[1] | 34764 | 1 | T2 | 270 | T6 | 386 | T23 | 302 | ||||
others[2] | 34959 | 1 | T2 | 301 | T6 | 401 | T23 | 323 | ||||
others[3] | 58608 | 1 | T2 | 506 | T6 | 669 | T23 | 474 | ||||
false | 17994 | 1 | T2 | 50 | T5 | 26 | T6 | 50 | ||||
true | 27710 | 1 | T1 | 3 | T2 | 52 | T3 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35098 | 1 | T2 | 307 | T6 | 432 | T23 | 280 | ||||
others[1] | 35326 | 1 | T2 | 319 | T6 | 394 | T23 | 308 | ||||
others[2] | 34847 | 1 | T2 | 284 | T6 | 418 | T23 | 305 | ||||
others[3] | 58341 | 1 | T2 | 485 | T6 | 643 | T23 | 514 | ||||
false | 11596 | 1 | T2 | 50 | T5 | 13 | T6 | 50 | ||||
true | 21369 | 1 | T1 | 3 | T2 | 52 | T3 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 668 | 1 | T8 | 1 | T37 | 1 | T39 | 1 | ||||
others[1] | 711 | 1 | T8 | 3 | T14 | 1 | T25 | 1 | ||||
others[2] | 656 | 1 | T8 | 3 | T39 | 1 | T15 | 9 | ||||
others[3] | 1115 | 1 | T8 | 3 | T14 | 1 | T38 | 1 | ||||
false | 13249 | 1 | T1 | 3 | T2 | 2 | T3 | 4 | ||||
true | 3977 | 1 | T8 | 12 | T14 | 9 | T25 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |