Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	26036253	12972	0	0
intr_enable_rd_A	26036253	34437	0	0
reset_en_rd_A	26036253	1438	0	0
reset_en_regwen_rd_A	26036253	1196	0	0
wake_info_capture_dis_rd_A	26036253	1103	0	0
wakeup_en_rd_A	26036253	2429	0	0
wakeup_en_regwen_rd_A	26036253	1070	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26036253	12972	0	0
T11	15764	0	0	0
T15	483991	48	0	0
T17	1577	0	0	0
T21	456133	23	0	0
T22	0	17	0	0
T23	34887	0	0	0
T29	0	5	0	0
T32	0	28	0	0
T40	4140	0	0	0
T41	58033	0	0	0
T42	5012	0	0	0
T64	9358	0	0	0
T80	0	15	0	0
T81	0	32	0	0
T97	1581	0	0	0
T135	0	28	0	0
T136	0	104	0	0
T137	0	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26036253	34437	0	0
T7	3274	56	0	0
T8	106617	0	0	0
T9	7064	0	0	0
T10	1452	0	0	0
T14	5411	0	0	0
T16	1311	0	0	0
T23	0	158	0	0
T25	3932	0	0	0
T37	0	19	0	0
T41	0	243	0	0
T42	0	60	0	0
T43	1900	0	0	0
T44	8509	84	0	0
T45	1869	11	0	0
T64	0	32	0	0
T98	0	12	0	0
T100	0	44	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26036253	1438	0	0
T88	0	13	0	0
T137	317048	1	0	0
T138	0	8	0	0
T139	0	10	0	0
T140	0	12	0	0
T141	0	5	0	0
T142	0	1	0	0
T143	0	8	0	0
T144	0	1	0	0
T145	0	6	0	0
T146	1443	0	0	0
T147	2016	0	0	0
T148	2896	0	0	0
T149	1766	0	0	0
T150	36378	0	0	0
T151	8017	0	0	0
T152	54197	0	0	0
T153	5760	0	0	0
T154	3220	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26036253	1196	0	0
T82	0	12	0	0
T88	0	4	0	0
T137	317048	1	0	0
T138	0	18	0	0
T139	0	5	0	0
T140	0	5	0	0
T141	0	10	0	0
T143	0	8	0	0
T144	0	3	0	0
T145	0	3	0	0
T146	1443	0	0	0
T147	2016	0	0	0
T148	2896	0	0	0
T149	1766	0	0	0
T150	36378	0	0	0
T151	8017	0	0	0
T152	54197	0	0	0
T153	5760	0	0	0
T154	3220	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26036253	1103	0	0
T57	0	7	0	0
T66	0	3	0	0
T88	0	18	0	0
T138	168581	9	0	0
T139	0	11	0	0
T140	0	8	0	0
T141	0	3	0	0
T143	0	14	0	0
T144	0	7	0	0
T155	0	2	0	0
T156	6632	0	0	0
T157	17683	0	0	0
T158	4646	0	0	0
T159	2313	0	0	0
T160	3108	0	0	0
T161	15180	0	0	0
T162	3995	0	0	0
T163	2073	0	0	0
T164	2241	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26036253	2429	0	0
T57	0	6	0	0
T82	0	9	0	0
T88	0	19	0	0
T137	317048	6	0	0
T138	0	6	0	0
T139	0	3	0	0
T140	0	11	0	0
T143	0	7	0	0
T144	0	28	0	0
T145	0	6	0	0
T146	1443	0	0	0
T147	2016	0	0	0
T148	2896	0	0	0
T149	1766	0	0	0
T150	36378	0	0	0
T151	8017	0	0	0
T152	54197	0	0	0
T153	5760	0	0	0
T154	3220	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26036253	1070	0	0
T82	0	3	0	0
T88	0	13	0	0
T137	317048	7	0	0
T138	0	4	0	0
T139	0	7	0	0
T140	0	16	0	0
T141	0	3	0	0
T143	0	6	0	0
T144	0	6	0	0
T145	0	9	0	0
T146	1443	0	0	0
T147	2016	0	0	0
T148	2896	0	0	0
T149	1766	0	0	0
T150	36378	0	0	0
T151	8017	0	0	0
T152	54197	0	0	0
T153	5760	0	0	0
T154	3220	0	0	0