Unified Coverage Report :: Module

Module : prim_subreg

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wake_status_val_0	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_wake_status_val_1	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_wake_status_val_2	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_wake_status_val_3	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_wake_status_val_4	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_wake_status_val_5	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_reset_status_val_0	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_reset_status_val_1	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_escalate_reset_status	65.24	85.71	50.00			60.00
tb.dut.u_reg.u_intr_state	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_low_power_hint	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_core_clk_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_io_clk_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_usb_clk_en_lp	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_usb_clk_en_active	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_control_main_pd_n	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_cfg_cdc_sync	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_wakeup_en_regwen	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_wakeup_en_en_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_wakeup_en_en_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_wakeup_en_en_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_wakeup_en_en_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_wakeup_en_en_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_wakeup_en_en_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_reset_en_regwen	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_reset_en_en_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_reset_en_en_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_wake_info_capture_dis	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fault_status_reg_intg_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fault_status_esc_timeout	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fault_status_main_pd_glitch	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_wake_status_val_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.24	85.71	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.59	77.78	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.u_reg.u_wake_status_val_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.24	85.71	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.59	77.78	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.u_reg.u_wake_status_val_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.24	85.71	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.59	77.78	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.u_reg.u_wake_status_val_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.24	85.71	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.59	77.78	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.u_reg.u_wake_status_val_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.24	85.71	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.59	77.78	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.u_reg.u_wake_status_val_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.24	85.71	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.59	77.78	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.u_reg.u_reset_status_val_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.24	85.71	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.59	77.78	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.u_reg.u_reset_status_val_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.24	85.71	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.59	77.78	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.u_reg.u_escalate_reset_status

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.24	85.71	50.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.59	77.78	50.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.u_reg.u_intr_state

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00

Module Instance : tb.dut.u_reg.u_intr_enable

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_control_low_power_hint

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_control_core_clk_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_control_io_clk_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_control_usb_clk_en_lp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_control_usb_clk_en_active

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_control_main_pd_n

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_cfg_cdc_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_wakeup_en_regwen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00

Module Instance : tb.dut.u_reg.u_wakeup_en_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_wakeup_en_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_wakeup_en_en_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_wakeup_en_en_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_wakeup_en_en_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_wakeup_en_en_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_reset_en_regwen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00

Module Instance : tb.dut.u_reg.u_reset_en_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_reset_en_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_wake_info_capture_dis

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_fault_status_reg_intg_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	88.89	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.u_reg.u_fault_status_esc_timeout

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	88.89	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.u_reg.u_fault_status_main_pd_glitch

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00

Line Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Module : prim_subreg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

Branch Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_wake_status_val_0

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wake_status_val_0

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wake_status_val_0

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_wake_status_val_1

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wake_status_val_1

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wake_status_val_1

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_wake_status_val_2

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wake_status_val_2

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wake_status_val_2

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_wake_status_val_3

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wake_status_val_3

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wake_status_val_3

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_wake_status_val_4

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wake_status_val_4

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wake_status_val_4

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_wake_status_val_5

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wake_status_val_5

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wake_status_val_5

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_reset_status_val_0

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_reset_status_val_0

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_reset_status_val_0

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_reset_status_val_1

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_reset_status_val_1

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_reset_status_val_1

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_escalate_reset_status

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_escalate_reset_status

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_escalate_reset_status

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_intr_state

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_intr_state

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_intr_state

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_intr_enable

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_control_low_power_hint

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_control_low_power_hint

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

Branch Coverage for Instance : tb.dut.u_reg.u_control_low_power_hint

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_control_core_clk_en

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_control_core_clk_en

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_control_core_clk_en

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_control_io_clk_en

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_control_io_clk_en

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_control_io_clk_en

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_control_usb_clk_en_lp

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_control_usb_clk_en_lp

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_control_usb_clk_en_lp

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_control_usb_clk_en_active

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_control_usb_clk_en_active

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_control_usb_clk_en_active

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_control_main_pd_n

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_control_main_pd_n

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_control_main_pd_n

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cfg_cdc_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_cfg_cdc_sync

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_cdc_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_wakeup_en_regwen

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wakeup_en_regwen

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T62,T52,T63

Branch Coverage for Instance : tb.dut.u_reg.u_wakeup_en_regwen

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T62,T52,T63
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T62,T52,T63
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_0

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_0

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_0

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_1

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_1

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_1

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_2

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_2

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_2

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_3

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_3

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_3

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_4

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_4

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_4

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_5

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_5

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_wakeup_en_en_5

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_reset_en_regwen

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_reset_en_regwen

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T62,T52,T63

Branch Coverage for Instance : tb.dut.u_reg.u_reset_en_regwen

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T62,T52,T63
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T62,T52,T63
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_reset_en_en_0

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_reset_en_en_0

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_reset_en_en_0

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_reset_en_en_1

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_reset_en_en_1

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_reset_en_en_1

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_wake_info_capture_dis

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wake_info_capture_dis

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_wake_info_capture_dis

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_reg_intg_err

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_fault_status_reg_intg_err

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T19,T20

Branch Coverage for Instance : tb.dut.u_reg.u_fault_status_reg_intg_err

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T18,T19,T20
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_esc_timeout

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_fault_status_esc_timeout

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T12,T13

Branch Coverage for Instance : tb.dut.u_reg.u_fault_status_esc_timeout

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_fault_status_main_pd_glitch

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_fault_status_main_pd_glitch

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_fault_status_main_pd_glitch

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3