Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	25539198	51239	0	0
IoStatusRise_A	25539198	57010	0	0
MainStatusFall_A	25539198	51239	0	0
MainStatusRise_A	25539198	57009	0	0
UsbStatusFall_A	25539198	35748	0	0
UsbStatusRise_A	25539198	40227	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25539198	51239	0	0
T2	20503	85	0	0
T3	2861	0	0	0
T4	1091	2	0	0
T5	4435	22	0	0
T6	58746	89	0	0
T7	3274	20	0	0
T8	106617	208	0	0
T9	7064	7	0	0
T10	1452	4	0	0
T14	5411	18	0	0
T44	0	20	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25539198	57010	0	0
T1	1281	3	0	0
T2	20503	87	0	0
T3	2861	4	0	0
T4	1091	3	0	0
T5	4435	24	0	0
T6	58746	90	0	0
T7	3274	21	0	0
T8	106617	231	0	0
T9	7064	8	0	0
T10	1452	5	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25539198	51239	0	0
T2	20503	85	0	0
T3	2861	0	0	0
T4	1091	2	0	0
T5	4435	22	0	0
T6	58746	89	0	0
T7	3274	20	0	0
T8	106617	208	0	0
T9	7064	7	0	0
T10	1452	4	0	0
T14	5411	18	0	0
T44	0	20	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25539198	57009	0	0
T1	1281	3	0	0
T2	20503	87	0	0
T3	2861	4	0	0
T4	1091	3	0	0
T5	4435	24	0	0
T6	58746	90	0	0
T7	3274	21	0	0
T8	106617	231	0	0
T9	7064	8	0	0
T10	1452	5	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25539198	35748	0	0
T2	20503	40	0	0
T3	2861	0	0	0
T4	1091	2	0	0
T5	4435	12	0	0
T6	58746	30	0	0
T7	3274	19	0	0
T8	106617	152	0	0
T9	7064	4	0	0
T10	1452	4	0	0
T14	5411	18	0	0
T44	0	8	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25539198	40227	0	0
T1	1281	3	0	0
T2	20503	42	0	0
T3	2861	4	0	0
T4	1091	3	0	0
T5	4435	13	0	0
T6	58746	31	0	0
T7	3274	19	0	0
T8	106617	168	0	0
T9	7064	4	0	0
T10	1452	5	0	0