Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	25539198	56616	0	0
RomAllowCheckGoodState_A	25539198	56668	0	0
RomBlockActiveState_A	25539198	28874	0	0
RomBlockCheckGoodState_A	25539198	411520	0	0
RomIntgChkDisFalse_A	25539198	24923233	0	0
RomIntgChkDisTrue_A	25539198	113431	0	0
RstreqChkEsctimeout_A	25539198	4244	0	0
RstreqChkFsmterm_A	25539198	180	0	0
RstreqChkGlbesc_A	25539198	4244	0	0
RstreqChkMainpd_A	25539198	1055316	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25539198	56616	0	0
T1	1281	3	0	0
T2	20503	87	0	0
T3	2861	4	0	0
T4	1091	3	0	0
T5	4435	24	0	0
T6	58746	90	0	0
T7	3274	21	0	0
T8	106617	231	0	0
T9	7064	8	0	0
T10	1452	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25539198	56668	0	0
T1	1281	3	0	0
T2	20503	87	0	0
T3	2861	4	0	0
T4	1091	3	0	0
T5	4435	24	0	0
T6	58746	90	0	0
T7	3274	21	0	0
T8	106617	231	0	0
T9	7064	8	0	0
T10	1452	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25539198	28874	0	0
T2	20503	4	0	0
T3	2861	0	0	0
T4	1091	0	0	0
T5	4435	0	0	0
T6	58746	0	0	0
T7	3274	0	0	0
T8	106617	0	0	0
T9	7064	0	0	0
T10	1452	0	0	0
T14	5411	0	0	0
T31	0	377	0	0
T36	0	13	0	0
T51	0	168	0	0
T165	0	572	0	0
T166	0	216	0	0
T167	0	17	0	0
T168	0	130	0	0
T169	0	134	0	0
T170	0	153	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25539198	411520	0	0
T2	20503	1327	0	0
T3	2861	0	0	0
T4	1091	0	0	0
T5	4435	298	0	0
T6	58746	4054	0	0
T7	3274	0	0	0
T8	106617	481	0	0
T9	7064	0	0	0
T10	1452	0	0	0
T14	5411	0	0	0
T15	0	2820	0	0
T21	0	4344	0	0
T22	0	2342	0	0
T23	0	2247	0	0
T24	0	922	0	0
T99	0	322	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25539198	24923233	0	0
T1	1281	1025	0	0
T2	20503	19753	0	0
T3	2861	2555	0	0
T4	1091	1026	0	0
T5	4435	4296	0	0
T6	58746	58681	0	0
T7	3274	3187	0	0
T8	106617	104852	0	0
T9	7064	6974	0	0
T10	1452	1118	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25539198	113431	0	0
T2	20503	583	0	0
T3	2861	0	0	0
T4	1091	0	0	0
T5	4435	0	0	0
T6	58746	0	0	0
T7	3274	0	0	0
T8	106617	0	0	0
T9	7064	0	0	0
T10	1452	0	0	0
T14	5411	0	0	0
T23	0	609	0	0
T24	0	178	0	0
T31	0	782	0	0
T50	0	75	0	0
T51	0	784	0	0
T165	0	108	0	0
T166	0	114	0	0
T168	0	1090	0	0
T171	0	300	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25539198	4244	0	0
T3	2861	3	0	0
T4	1091	0	0	0
T5	4435	0	0	0
T6	58746	0	0	0
T7	3274	0	0	0
T8	106617	17	0	0
T9	7064	0	0	0
T10	1452	0	0	0
T14	5411	7	0	0
T15	0	57	0	0
T25	0	6	0	0
T38	0	4	0	0
T39	0	7	0	0
T40	0	6	0	0
T43	1900	5	0	0
T46	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25539198	180	0	0
T18	46112	40	0	0
T19	0	20	0	0
T20	0	40	0	0
T26	0	40	0	0
T27	0	40	0	0
T28	1542	0	0	0
T29	56543	0	0	0
T30	1349	0	0	0
T31	1985	0	0	0
T32	512536	0	0	0
T33	10222	0	0	0
T34	3475	0	0	0
T35	7188	0	0	0
T36	23380	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25539198	4244	0	0
T3	2861	3	0	0
T4	1091	0	0	0
T5	4435	0	0	0
T6	58746	0	0	0
T7	3274	0	0	0
T8	106617	17	0	0
T9	7064	0	0	0
T10	1452	0	0	0
T14	5411	7	0	0
T15	0	57	0	0
T25	0	6	0	0
T38	0	4	0	0
T39	0	7	0	0
T40	0	6	0	0
T43	1900	5	0	0
T46	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25539198	1055316	0	0
T1	1281	11	0	0
T2	20503	1709	0	0
T3	2861	0	0	0
T4	1091	0	0	0
T5	4435	406	0	0
T6	58746	5641	0	0
T7	3274	0	0	0
T8	106617	3427	0	0
T9	7064	0	0	0
T10	1452	0	0	0
T14	0	672	0	0
T16	0	20	0	0
T25	0	157	0	0
T37	0	194	0	0
T38	0	514	0	0