Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_wakeup_ctrl_cg_wrap::wakeup_ctrl_cg

Group : pwrmgr_env_pkg::pwrmgr_wakeup_ctrl_cg_wrap::wakeup_ctrl_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

6 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
WakeupAonTimer_ctrl_cg	100.00	1	100	1	64	64
WakeupDbgCable_ctrl_cg	100.00	1	100	1	64	64
WakeupPin_ctrl_cg	100.00	1	100	1	64	64
WakeupSensorCtrl_ctrl_cg	100.00	1	100	1	64	64
WakeupSysrst_ctrl_cg	100.00	1	100	1	64	64
WakeupUsb_ctrl_cg	100.00	1	100	1	64	64

---

Group Instance : WakeupAonTimer_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupAonTimer_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupAonTimer_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupAonTimer_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupDbgCable_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupDbgCable_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupDbgCable_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupDbgCable_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupPin_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupPin_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupPin_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupPin_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupSensorCtrl_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupSensorCtrl_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupSensorCtrl_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupSensorCtrl_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupSysrst_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupSysrst_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupSysrst_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupSysrst_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupUsb_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupUsb_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupUsb_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupUsb_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6628

1

T3

7

T5

5

T6

1

auto[1]

18155

1

T3

6

T5

5

T6

3

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11301

1

T3

3

T5

8

T6

3

auto[1]

13482

1

T3

10

T5

2

T6

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11843

1

T3

8

T5

7

T6

3

auto[1]

12940

1

T3

5

T5

3

T6

1

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1525	1			T3	2		T5	2		T6	1
auto[0]	auto[0]	auto[1]	1548	1			T5	1		T7	1		T10	5
auto[0]	auto[1]	auto[0]	4321	1			T3	1		T5	3		T6	1
auto[0]	auto[1]	auto[1]	3907	1			T5	2		T6	1		T7	1
auto[1]	auto[0]	auto[0]	1544	1			T3	3		T5	2		T10	5
auto[1]	auto[0]	auto[1]	2011	1			T3	2		T7	2		T10	5
auto[1]	auto[1]	auto[0]	4453	1			T3	2		T6	1		T7	1
auto[1]	auto[1]	auto[1]	5474	1			T3	3		T7	1		T10	7

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6628

1

T3

7

T5

5

T6

1

auto[1]

18155

1

T3

6

T5

5

T6

3

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11075

1

T3

7

T5

3

T6

3

auto[1]

13708

1

T3

6

T5

7

T6

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11734

1

T3

8

T5

2

T6

2

auto[1]

13049

1

T3

5

T5

8

T6

2

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1543	1			T3	4		T6	1		T7	3
auto[0]	auto[0]	auto[1]	1501	1			T5	1		T10	9		T27	1
auto[0]	auto[1]	auto[0]	4117	1			T3	1		T10	3		T20	6
auto[0]	auto[1]	auto[1]	3914	1			T3	2		T5	2		T6	2
auto[1]	auto[0]	auto[0]	1482	1			T3	2		T10	7		T27	1
auto[1]	auto[0]	auto[1]	2102	1			T3	1		T5	4		T10	4
auto[1]	auto[1]	auto[0]	4592	1			T3	1		T5	2		T6	1
auto[1]	auto[1]	auto[1]	5532	1			T3	2		T5	1		T7	3

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6628

1

T3

7

T5

5

T6

1

auto[1]

18155

1

T3

6

T5

5

T6

3

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11209

1

T3

5

T5

4

T6

2

auto[1]

13574

1

T3

8

T5

6

T6

2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11737

1

T3

9

T5

4

T6

4

auto[1]

13046

1

T3

4

T5

6

T7

1

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1599	1			T3	1		T6	1		T7	3
auto[0]	auto[0]	auto[1]	1526	1			T3	1		T5	3		T10	8
auto[0]	auto[1]	auto[0]	4150	1			T3	1		T6	1		T7	2
auto[0]	auto[1]	auto[1]	3934	1			T3	2		T5	1		T10	6
auto[1]	auto[0]	auto[0]	1468	1			T3	4		T5	2		T10	6
auto[1]	auto[0]	auto[1]	2035	1			T3	1		T10	6		T27	2
auto[1]	auto[1]	auto[0]	4520	1			T3	3		T5	2		T6	2
auto[1]	auto[1]	auto[1]	5551	1			T5	2		T7	1		T10	5

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6628

1

T3

7

T5

5

T6

1

auto[1]

18155

1

T3

6

T5

5

T6

3

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11151

1

T3

9

T5

4

T6

1

auto[1]

13632

1

T3

4

T5

6

T6

3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11642

1

T3

6

T5

4

T6

1

auto[1]

13141

1

T3

7

T5

6

T6

3

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1506	1			T3	1		T5	1		T7	2
auto[0]	auto[0]	auto[1]	1534	1			T3	4		T5	2		T10	5
auto[0]	auto[1]	auto[0]	4178	1			T3	3		T10	1		T20	15
auto[0]	auto[1]	auto[1]	3933	1			T3	1		T5	1		T6	1
auto[1]	auto[0]	auto[0]	1498	1			T3	2		T5	1		T10	2
auto[1]	auto[0]	auto[1]	2090	1			T5	1		T6	1		T7	1
auto[1]	auto[1]	auto[0]	4460	1			T5	2		T6	1		T7	2
auto[1]	auto[1]	auto[1]	5584	1			T3	2		T5	2		T6	1

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6628

1

T3

7

T5

5

T6

1

auto[1]

18155

1

T3

6

T5

5

T6

3

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11145

1

T3

7

T5

5

T6

2

auto[1]

13638

1

T3

6

T5

5

T6

2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11685

1

T3

6

T5

5

T6

1

auto[1]

13098

1

T3

7

T5

5

T6

3

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1533	1			T3	1		T5	2		T7	2
auto[0]	auto[0]	auto[1]	1543	1			T3	3		T5	1		T10	4
auto[0]	auto[1]	auto[0]	4178	1			T3	1		T7	1		T10	6
auto[0]	auto[1]	auto[1]	3891	1			T3	2		T5	2		T6	2
auto[1]	auto[0]	auto[0]	1486	1			T3	2		T6	1		T10	3
auto[1]	auto[0]	auto[1]	2066	1			T3	1		T5	2		T7	1
auto[1]	auto[1]	auto[0]	4488	1			T3	2		T5	3		T7	2
auto[1]	auto[1]	auto[1]	5598	1			T3	1		T6	1		T10	5

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6628

1

T3

7

T5

5

T6

1

auto[1]

18155

1

T3

6

T5

5

T6

3

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11290

1

T3

4

T5

5

T6

1

auto[1]

13493

1

T3

9

T5

5

T6

3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11800

1

T3

5

T5

4

T6

2

auto[1]

12983

1

T3

8

T5

6

T6

2

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1522	1			T3	1		T7	1		T10	11
auto[0]	auto[0]	auto[1]	1561	1			T5	2		T7	1		T10	6
auto[0]	auto[1]	auto[0]	4245	1			T3	2		T5	2		T6	1
auto[0]	auto[1]	auto[1]	3962	1			T3	1		T5	1		T10	3
auto[1]	auto[0]	auto[0]	1477	1			T3	2		T5	1		T6	1
auto[1]	auto[0]	auto[1]	2068	1			T3	4		T5	2		T7	1
auto[1]	auto[1]	auto[0]	4556	1			T5	1		T7	1		T10	6
auto[1]	auto[1]	auto[1]	5392	1			T3	3		T5	1		T6	2