Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	470757	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

183830

1

T1

38

T3

71

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	343469	1			T1	103		T2	1		T3	111
values[0x0]	155283	1			T1	25		T3	69		T5	40
values[0x1]	155835	1			T1	29		T3	57		T5	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	372734	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

281853

1

T1

56

T3

101

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1804	1			T10	6		T20	4		T14	21
valid_sources[0x01]	2076	1			T1	1		T3	4		T10	6
valid_sources[0x02]	1913	1			T3	1		T6	1		T10	7
valid_sources[0x03]	2197	1			T1	1		T3	2		T7	1
valid_sources[0x04]	2186	1			T10	6		T14	24		T29	15
valid_sources[0x05]	1941	1			T1	1		T6	1		T10	3
valid_sources[0x06]	1694	1			T6	1		T10	9		T20	1
valid_sources[0x07]	2187	1			T6	1		T10	3		T20	1
valid_sources[0x08]	3013	1			T10	4		T27	1		T14	61
valid_sources[0x09]	2350	1			T1	1		T3	2		T10	2
valid_sources[0x0a]	1851	1			T3	4		T6	2		T10	3
valid_sources[0x0b]	2073	1			T1	2		T10	1		T20	20
valid_sources[0x0c]	2632	1			T6	2		T7	9		T10	7
valid_sources[0x0d]	2161	1			T10	6		T20	4		T15	7
valid_sources[0x0e]	2167	1			T10	10		T20	4		T14	6
valid_sources[0x0f]	2004	1			T10	5		T20	1		T27	2
valid_sources[0x10]	2177	1			T1	1		T10	9		T20	3
valid_sources[0x11]	1816	1			T1	1		T10	5		T20	3
valid_sources[0x12]	2136	1			T10	4		T15	1		T14	7
valid_sources[0x13]	2240	1			T6	2		T10	7		T27	1
valid_sources[0x14]	2355	1			T10	2		T20	4		T14	7
valid_sources[0x15]	1678	1			T10	1		T20	1		T14	32
valid_sources[0x16]	4382	1			T6	1		T10	4		T20	1
valid_sources[0x17]	2161	1			T1	1		T10	2		T15	2
valid_sources[0x18]	3914	1			T3	4		T5	4		T10	2
valid_sources[0x19]	2009	1			T1	2		T10	8		T20	1
valid_sources[0x1a]	1884	1			T10	3		T20	16		T27	2
valid_sources[0x1b]	2341	1			T5	22		T6	1		T10	5
valid_sources[0x1c]	2635	1			T10	7		T20	4		T15	4
valid_sources[0x1d]	4117	1			T1	4		T6	1		T10	6
valid_sources[0x1e]	1768	1			T10	1		T27	1		T14	38
valid_sources[0x1f]	1822	1			T3	1		T10	3		T20	4
valid_sources[0x20]	2099	1			T1	3		T3	1		T10	3
valid_sources[0x21]	1796	1			T1	2		T10	2		T27	1
valid_sources[0x22]	2305	1			T3	10		T10	3		T14	17
valid_sources[0x23]	2545	1			T3	2		T10	4		T20	12
valid_sources[0x24]	3222	1			T3	1		T10	4		T20	8
valid_sources[0x25]	2441	1			T6	1		T10	2		T20	1
valid_sources[0x26]	2300	1			T10	5		T20	1		T27	1
valid_sources[0x27]	1882	1			T3	1		T10	6		T20	3
valid_sources[0x28]	1874	1			T6	1		T15	1		T14	60
valid_sources[0x29]	2547	1			T10	3		T20	1		T14	47
valid_sources[0x2a]	1813	1			T3	5		T6	2		T10	7
valid_sources[0x2b]	2700	1			T10	5		T20	4		T27	1
valid_sources[0x2c]	5048	1			T10	4		T20	1		T14	19
valid_sources[0x2d]	2056	1			T3	1		T10	9		T14	104
valid_sources[0x2e]	3055	1			T1	1		T7	1		T10	7
valid_sources[0x2f]	1966	1			T3	5		T10	5		T27	1
valid_sources[0x30]	3499	1			T6	1		T10	3		T20	1
valid_sources[0x31]	2337	1			T3	2		T5	5		T10	9
valid_sources[0x32]	3631	1			T10	1		T27	2		T15	6
valid_sources[0x33]	11194	1			T3	2		T10	3		T20	1
valid_sources[0x34]	1663	1			T10	1		T20	2		T27	2
valid_sources[0x35]	1880	1			T1	1		T3	4		T6	1
valid_sources[0x36]	2744	1			T10	3		T20	2		T27	1
valid_sources[0x37]	1964	1			T1	2		T6	2		T10	3
valid_sources[0x38]	2956	1			T1	2		T10	3		T20	1
valid_sources[0x39]	1824	1			T1	1		T10	1		T27	1
valid_sources[0x3a]	3106	1			T3	1		T10	4		T20	2
valid_sources[0x3b]	1863	1			T6	1		T7	3		T10	3
valid_sources[0x3c]	6041	1			T10	5		T27	1		T14	20
valid_sources[0x3d]	1897	1			T1	3		T3	4		T6	1
valid_sources[0x3e]	1764	1			T1	1		T10	5		T20	3
valid_sources[0x3f]	3316	1			T6	1		T10	4		T14	21
valid_sources[0x40]	2594	1			T1	2		T10	9		T20	2
valid_sources[0x41]	1698	1			T1	1		T3	1		T10	2
valid_sources[0x42]	4263	1			T10	4		T20	7		T14	11
valid_sources[0x43]	1829	1			T10	2		T20	5		T14	16
valid_sources[0x44]	2300	1			T1	1		T3	1		T10	5
valid_sources[0x45]	2006	1			T7	5		T10	3		T20	9
valid_sources[0x46]	3677	1			T10	1		T20	6		T27	3
valid_sources[0x47]	1764	1			T6	1		T10	3		T20	2
valid_sources[0x48]	1873	1			T3	1		T6	1		T10	5
valid_sources[0x49]	1925	1			T3	7		T10	2		T27	1
valid_sources[0x4a]	1930	1			T3	1		T10	2		T20	8
valid_sources[0x4b]	4374	1			T10	1		T20	7		T14	72
valid_sources[0x4c]	6899	1			T3	1		T10	2		T20	5
valid_sources[0x4d]	2169	1			T5	3		T10	3		T20	1
valid_sources[0x4e]	1770	1			T3	2		T10	2		T27	1
valid_sources[0x4f]	1840	1			T1	2		T6	1		T20	5
valid_sources[0x50]	2959	1			T6	1		T10	6		T20	12
valid_sources[0x51]	1891	1			T10	4		T27	1		T15	1
valid_sources[0x52]	2012	1			T10	1		T20	5		T14	51
valid_sources[0x53]	3504	1			T10	3		T14	14		T55	2
valid_sources[0x54]	1937	1			T1	1		T6	1		T10	3
valid_sources[0x55]	1852	1			T1	1		T10	4		T14	44
valid_sources[0x56]	1953	1			T10	11		T20	1		T27	1
valid_sources[0x57]	6137	1			T1	1		T10	4		T20	4
valid_sources[0x58]	2494	1			T5	26		T6	1		T7	21
valid_sources[0x59]	2728	1			T20	7		T14	32		T55	1
valid_sources[0x5a]	3007	1			T3	2		T10	2		T20	10
valid_sources[0x5b]	2730	1			T10	3		T20	1		T14	18
valid_sources[0x5c]	2169	1			T6	1		T10	2		T14	25
valid_sources[0x5d]	2045	1			T1	3		T10	2		T20	7
valid_sources[0x5e]	2234	1			T1	2		T10	4		T20	10
valid_sources[0x5f]	2248	1			T3	1		T6	2		T10	11
valid_sources[0x60]	2056	1			T1	1		T6	1		T10	5
valid_sources[0x61]	2816	1			T6	1		T7	9		T10	1
valid_sources[0x62]	1915	1			T3	3		T6	1		T10	3
valid_sources[0x63]	1946	1			T1	1		T10	7		T14	42
valid_sources[0x64]	2203	1			T6	1		T10	3		T20	5
valid_sources[0x65]	3534	1			T1	1		T10	3		T27	1
valid_sources[0x66]	1841	1			T1	1		T10	3		T20	5
valid_sources[0x67]	2232	1			T1	2		T3	7		T6	1
valid_sources[0x68]	2045	1			T3	1		T10	4		T27	1
valid_sources[0x69]	1780	1			T1	3		T6	1		T10	5
valid_sources[0x6a]	2298	1			T6	1		T10	4		T20	17
valid_sources[0x6b]	2463	1			T10	7		T14	35		T127	2
valid_sources[0x6c]	1964	1			T10	3		T20	2		T27	3
valid_sources[0x6d]	2194	1			T6	2		T10	9		T20	6
valid_sources[0x6e]	1960	1			T3	2		T6	1		T10	4
valid_sources[0x6f]	1864	1			T1	1		T10	1		T20	2
valid_sources[0x70]	2532	1			T1	3		T10	4		T20	7
valid_sources[0x71]	2047	1			T1	4		T3	3		T10	6
valid_sources[0x72]	2107	1			T6	1		T10	4		T14	55
valid_sources[0x73]	3061	1			T3	9		T5	3		T10	4
valid_sources[0x74]	2262	1			T10	4		T20	4		T14	73
valid_sources[0x75]	2262	1			T1	1		T6	1		T10	5
valid_sources[0x76]	4288	1			T1	4		T6	1		T10	6
valid_sources[0x77]	2631	1			T6	1		T10	2		T20	7
valid_sources[0x78]	4614	1			T1	1		T6	1		T10	9
valid_sources[0x79]	2678	1			T6	1		T10	2		T13	11
valid_sources[0x7a]	3570	1			T7	2		T10	1		T20	6
valid_sources[0x7b]	1967	1			T3	1		T6	1		T10	1
valid_sources[0x7c]	1907	1			T10	8		T14	23		T127	1
valid_sources[0x7d]	2190	1			T1	3		T10	8		T20	3
valid_sources[0x7e]	2926	1			T1	1		T3	5		T5	8
valid_sources[0x7f]	2028	1			T10	1		T20	4		T14	47
valid_sources[0x80]	2929	1			T3	2		T10	2		T20	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

93756

1

T1

23

T3

34

T4

1

values[0x0]

all_enables

biggest_size

58336

1

T1

8

T3

24

T5

24

values[0x1]

all_enables

biggest_size

31738

1

T1

7

T3

13

T5

6