SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34787 | 1 | T20 | 300 | T21 | 309 | T22 | 305 | ||||
others[1] | 34977 | 1 | T20 | 324 | T21 | 299 | T22 | 287 | ||||
others[2] | 35084 | 1 | T20 | 281 | T21 | 305 | T22 | 296 | ||||
others[3] | 58627 | 1 | T20 | 484 | T21 | 489 | T22 | 501 | ||||
false | 16903 | 1 | T10 | 6 | T20 | 50 | T14 | 122 | ||||
true | 26497 | 1 | T1 | 3 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35187 | 1 | T20 | 294 | T21 | 295 | T22 | 306 | ||||
others[1] | 34939 | 1 | T20 | 321 | T21 | 278 | T22 | 298 | ||||
others[2] | 34993 | 1 | T20 | 303 | T21 | 297 | T22 | 300 | ||||
others[3] | 58526 | 1 | T20 | 486 | T21 | 544 | T22 | 501 | ||||
false | 11049 | 1 | T10 | 3 | T20 | 50 | T14 | 61 | ||||
true | 20697 | 1 | T1 | 3 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 634 | 1 | T14 | 2 | T23 | 1 | T127 | 7 | ||||
others[1] | 647 | 1 | T14 | 2 | T127 | 3 | T31 | 2 | ||||
others[2] | 643 | 1 | T1 | 1 | T14 | 8 | T127 | 4 | ||||
others[3] | 1084 | 1 | T1 | 1 | T14 | 7 | T23 | 2 | ||||
false | 12470 | 1 | T1 | 11 | T2 | 5 | T3 | 1 | ||||
true | 3482 | 1 | T1 | 6 | T14 | 58 | T23 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |