Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T14,T32

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	21542849	5690	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	21542849	231589	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	21542849	8904501	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	21542849	231609	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	21542849	5690	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	21542849	231589	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	21542849	8904501	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	21542849	231609	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	5690	0	0
T10	61746	5	0	0
T11	15151	0	0	0
T12	15767	0	0	0
T13	9462	0	0	0
T14	193138	30	0	0
T15	2855	0	0	0
T20	21461	15	0	0
T21	0	20	0	0
T22	0	21	0	0
T24	1498	0	0	0
T27	11460	0	0	0
T28	1414	0	0	0
T30	0	5	0	0
T32	0	11	0	0
T38	0	3	0	0
T69	0	22	0	0
T70	0	26	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	231589	0	0
T10	61746	668	0	0
T11	15151	0	0	0
T12	15767	0	0	0
T13	9462	0	0	0
T14	193138	1699	0	0
T15	2855	0	0	0
T20	21461	320	0	0
T21	0	471	0	0
T22	0	1128	0	0
T24	1498	0	0	0
T27	11460	0	0	0
T28	1414	0	0	0
T30	0	99	0	0
T32	0	600	0	0
T38	0	289	0	0
T69	0	1169	0	0
T70	0	1461	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	8904501	0	0
T3	6142	830	0	0
T4	828	0	0	0
T5	8877	3396	0	0
T6	3148	1480	0	0
T7	6260	2193	0	0
T8	3623	0	0	0
T9	1013	0	0	0
T10	61746	29071	0	0
T13	9462	0	0	0
T14	0	75651	0	0
T15	0	1287	0	0
T20	21461	8989	0	0
T27	0	6471	0	0
T29	0	1981	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	231609	0	0
T10	61746	668	0	0
T11	15151	0	0	0
T12	15767	0	0	0
T13	9462	0	0	0
T14	193138	1699	0	0
T15	2855	0	0	0
T20	21461	320	0	0
T21	0	471	0	0
T22	0	1128	0	0
T24	1498	0	0	0
T27	11460	0	0	0
T28	1414	0	0	0
T30	0	99	0	0
T32	0	596	0	0
T38	0	289	0	0
T69	0	1169	0	0
T70	0	1461	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	5690	0	0
T10	61746	5	0	0
T11	15151	0	0	0
T12	15767	0	0	0
T13	9462	0	0	0
T14	193138	30	0	0
T15	2855	0	0	0
T20	21461	15	0	0
T21	0	20	0	0
T22	0	21	0	0
T24	1498	0	0	0
T27	11460	0	0	0
T28	1414	0	0	0
T30	0	5	0	0
T32	0	11	0	0
T38	0	3	0	0
T69	0	22	0	0
T70	0	26	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	231589	0	0
T10	61746	668	0	0
T11	15151	0	0	0
T12	15767	0	0	0
T13	9462	0	0	0
T14	193138	1699	0	0
T15	2855	0	0	0
T20	21461	320	0	0
T21	0	471	0	0
T22	0	1128	0	0
T24	1498	0	0	0
T27	11460	0	0	0
T28	1414	0	0	0
T30	0	99	0	0
T32	0	600	0	0
T38	0	289	0	0
T69	0	1169	0	0
T70	0	1461	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	8904501	0	0
T3	6142	830	0	0
T4	828	0	0	0
T5	8877	3396	0	0
T6	3148	1480	0	0
T7	6260	2193	0	0
T8	3623	0	0	0
T9	1013	0	0	0
T10	61746	29071	0	0
T13	9462	0	0	0
T14	0	75651	0	0
T15	0	1287	0	0
T20	21461	8989	0	0
T27	0	6471	0	0
T29	0	1981	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	231609	0	0
T10	61746	668	0	0
T11	15151	0	0	0
T12	15767	0	0	0
T13	9462	0	0	0
T14	193138	1699	0	0
T15	2855	0	0	0
T20	21461	320	0	0
T21	0	471	0	0
T22	0	1128	0	0
T24	1498	0	0	0
T27	11460	0	0	0
T28	1414	0	0	0
T30	0	99	0	0
T32	0	596	0	0
T38	0	289	0	0
T69	0	1169	0	0
T70	0	1461	0	0