Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22105646	13993	0	0
intr_enable_rd_A	22105646	41336	0	0
reset_en_rd_A	22105646	1533	0	0
reset_en_regwen_rd_A	22105646	1324	0	0
wake_info_capture_dis_rd_A	22105646	1297	0	0
wakeup_en_rd_A	22105646	2466	0	0
wakeup_en_regwen_rd_A	22105646	1343	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22105646	13993	0	0
T12	15767	0	0	0
T14	193138	43	0	0
T18	0	160	0	0
T19	0	17	0	0
T23	3184	0	0	0
T24	1498	0	0	0
T29	3117	0	0	0
T37	1008	0	0	0
T45	0	47	0	0
T71	6924	0	0	0
T72	5786	0	0	0
T118	926	0	0	0
T120	0	13	0	0
T121	0	11	0	0
T122	0	21	0	0
T123	0	3	0	0
T124	0	21	0	0
T125	0	43	0	0
T126	2365	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22105646	41336	0	0
T3	6142	60	0	0
T4	828	0	0	0
T5	8877	0	0	0
T6	3148	0	0	0
T7	6260	0	0	0
T8	3623	0	0	0
T9	1013	0	0	0
T10	61746	292	0	0
T13	9462	0	0	0
T20	21461	0	0	0
T21	0	195	0	0
T22	0	106	0	0
T29	0	13	0	0
T30	0	28	0	0
T31	0	320	0	0
T34	0	3	0	0
T55	0	9	0	0
T127	0	95	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22105646	1533	0	0
T50	0	3	0	0
T76	0	8	0	0
T77	0	11	0	0
T128	252432	1	0	0
T129	0	14	0	0
T130	0	9	0	0
T131	0	7	0	0
T132	0	3	0	0
T133	0	2	0	0
T134	0	11	0	0
T135	8554	0	0	0
T136	3266	0	0	0
T137	17108	0	0	0
T138	1446	0	0	0
T139	1823	0	0	0
T140	1305	0	0	0
T141	3024	0	0	0
T142	3166	0	0	0
T143	5253	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22105646	1324	0	0
T50	0	2	0	0
T76	0	1	0	0
T77	0	4	0	0
T129	336206	3	0	0
T130	0	15	0	0
T131	0	8	0	0
T133	0	6	0	0
T134	0	20	0	0
T144	0	2	0	0
T145	0	15	0	0
T146	2547	0	0	0
T147	15869	0	0	0
T148	2716	0	0	0
T149	3100	0	0	0
T150	1597	0	0	0
T151	21711	0	0	0
T152	104876	0	0	0
T153	38202	0	0	0
T154	5807	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22105646	1297	0	0
T50	0	8	0	0
T76	0	1	0	0
T77	0	5	0	0
T129	336206	11	0	0
T130	0	5	0	0
T131	0	2	0	0
T133	0	4	0	0
T134	0	13	0	0
T145	0	2	0	0
T146	2547	0	0	0
T147	15869	0	0	0
T148	2716	0	0	0
T149	3100	0	0	0
T150	1597	0	0	0
T151	21711	0	0	0
T152	104876	0	0	0
T153	38202	0	0	0
T154	5807	0	0	0
T155	0	7	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22105646	2466	0	0
T50	0	3	0	0
T76	0	18	0	0
T77	0	3	0	0
T129	336206	12	0	0
T130	0	7	0	0
T131	0	9	0	0
T133	0	4	0	0
T134	0	16	0	0
T145	0	9	0	0
T146	2547	0	0	0
T147	15869	0	0	0
T148	2716	0	0	0
T149	3100	0	0	0
T150	1597	0	0	0
T151	21711	0	0	0
T152	104876	0	0	0
T153	38202	0	0	0
T154	5807	0	0	0
T155	0	20	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22105646	1343	0	0
T50	0	10	0	0
T57	0	52	0	0
T76	0	13	0	0
T77	0	7	0	0
T104	0	213	0	0
T129	336206	3	0	0
T130	0	19	0	0
T134	0	17	0	0
T145	0	7	0	0
T146	2547	0	0	0
T147	15869	0	0	0
T148	2716	0	0	0
T149	3100	0	0	0
T150	1597	0	0	0
T151	21711	0	0	0
T152	104876	0	0	0
T153	38202	0	0	0
T154	5807	0	0	0
T155	0	4	0	0