Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	21542849	48963	0	0
IoStatusRise_A	21542849	54614	0	0
MainStatusFall_A	21542849	48963	0	0
MainStatusRise_A	21542849	54614	0	0
UsbStatusFall_A	21542849	33882	0	0
UsbStatusRise_A	21542849	38229	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	48963	0	0
T1	6489	18	0	0
T2	855	0	0	0
T3	6142	13	0	0
T4	828	1	0	0
T5	8877	10	0	0
T6	3148	4	0	0
T7	6260	6	0	0
T8	3623	0	0	0
T9	1013	0	0	0
T10	61746	73	0	0
T13	0	30	0	0
T20	0	84	0	0
T27	0	11	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	54614	0	0
T1	6489	21	0	0
T2	855	5	0	0
T3	6142	14	0	0
T4	828	3	0	0
T5	8877	11	0	0
T6	3148	5	0	0
T7	6260	7	0	0
T8	3623	6	0	0
T9	1013	4	0	0
T10	61746	85	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	48963	0	0
T1	6489	18	0	0
T2	855	0	0	0
T3	6142	13	0	0
T4	828	1	0	0
T5	8877	10	0	0
T6	3148	4	0	0
T7	6260	6	0	0
T8	3623	0	0	0
T9	1013	0	0	0
T10	61746	73	0	0
T13	0	30	0	0
T20	0	84	0	0
T27	0	11	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	54614	0	0
T1	6489	21	0	0
T2	855	5	0	0
T3	6142	14	0	0
T4	828	3	0	0
T5	8877	11	0	0
T6	3148	5	0	0
T7	6260	7	0	0
T8	3623	6	0	0
T9	1013	4	0	0
T10	61746	85	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	33882	0	0
T1	6489	18	0	0
T2	855	0	0	0
T3	6142	10	0	0
T4	828	1	0	0
T5	8877	5	0	0
T6	3148	3	0	0
T7	6260	6	0	0
T8	3623	0	0	0
T9	1013	0	0	0
T10	61746	58	0	0
T13	0	30	0	0
T20	0	51	0	0
T27	0	9	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	38229	0	0
T1	6489	21	0	0
T2	855	5	0	0
T3	6142	10	0	0
T4	828	3	0	0
T5	8877	6	0	0
T6	3148	4	0	0
T7	6260	7	0	0
T8	3623	6	0	0
T9	1013	4	0	0
T10	61746	64	0	0