Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	21542849	54204	0	0
RomAllowCheckGoodState_A	21542849	54255	0	0
RomBlockActiveState_A	21542849	25761	0	0
RomBlockCheckGoodState_A	21542849	388117	0	0
RomIntgChkDisFalse_A	21542849	20836714	0	0
RomIntgChkDisTrue_A	21542849	213347	0	0
RstreqChkEsctimeout_A	21542849	3864	0	0
RstreqChkFsmterm_A	21542849	180	0	0
RstreqChkGlbesc_A	21542849	3864	0	0
RstreqChkMainpd_A	21542849	860874	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	54204	0	0
T1	6489	21	0	0
T2	855	5	0	0
T3	6142	14	0	0
T4	828	3	0	0
T5	8877	11	0	0
T6	3148	5	0	0
T7	6260	7	0	0
T8	3623	6	0	0
T9	1013	4	0	0
T10	61746	85	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	54255	0	0
T1	6489	21	0	0
T2	855	5	0	0
T3	6142	14	0	0
T4	828	3	0	0
T5	8877	11	0	0
T6	3148	5	0	0
T7	6260	7	0	0
T8	3623	6	0	0
T9	1013	4	0	0
T10	61746	85	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	25761	0	0
T11	15151	0	0	0
T12	15767	0	0	0
T14	193138	0	0	0
T15	2855	0	0	0
T20	21461	12	0	0
T21	0	13	0	0
T24	1498	0	0	0
T27	11460	0	0	0
T28	1414	0	0	0
T29	3117	0	0	0
T37	1008	0	0	0
T42	0	11	0	0
T156	0	583	0	0
T157	0	291	0	0
T158	0	1393	0	0
T159	0	49	0	0
T160	0	12	0	0
T161	0	16	0	0
T162	0	228	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	388117	0	0
T10	61746	69	0	0
T11	15151	0	0	0
T12	15767	0	0	0
T13	9462	0	0	0
T14	193138	1397	0	0
T15	2855	0	0	0
T18	0	5340	0	0
T20	21461	1258	0	0
T21	0	1272	0	0
T22	0	3258	0	0
T24	1498	0	0	0
T27	11460	0	0	0
T28	1414	0	0	0
T30	0	207	0	0
T32	0	341	0	0
T69	0	4113	0	0
T70	0	4149	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	20836714	0	0
T1	6489	6205	0	0
T2	855	515	0	0
T3	6142	6062	0	0
T4	828	700	0	0
T5	8877	8826	0	0
T6	3148	3048	0	0
T7	6260	6200	0	0
T8	3623	3193	0	0
T9	1013	676	0	0
T10	61746	60896	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	213347	0	0
T11	15151	0	0	0
T12	15767	0	0	0
T14	193138	0	0	0
T15	2855	0	0	0
T20	21461	16634	0	0
T21	0	199	0	0
T22	0	2249	0	0
T24	1498	0	0	0
T27	11460	0	0	0
T28	1414	0	0	0
T29	3117	0	0	0
T37	1008	0	0	0
T156	0	1064	0	0
T157	0	337	0	0
T158	0	191	0	0
T159	0	164	0	0
T161	0	238	0	0
T163	0	1067	0	0
T164	0	72	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	3864	0	0
T1	6489	6	0	0
T2	855	0	0	0
T3	6142	0	0	0
T4	828	1	0	0
T5	8877	0	0	0
T6	3148	0	0	0
T7	6260	0	0	0
T8	3623	0	0	0
T9	1013	0	0	0
T10	61746	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	10	0	0
T14	0	54	0	0
T23	0	6	0	0
T24	0	5	0	0
T31	0	15	0	0
T34	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	180	0	0
T11	15151	0	0	0
T12	15767	0	0	0
T13	9462	20	0	0
T14	193138	0	0	0
T15	2855	0	0	0
T16	0	40	0	0
T17	0	40	0	0
T20	21461	0	0	0
T24	1498	0	0	0
T25	0	40	0	0
T26	0	40	0	0
T27	11460	0	0	0
T28	1414	0	0	0
T29	3117	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	3864	0	0
T1	6489	6	0	0
T2	855	0	0	0
T3	6142	0	0	0
T4	828	1	0	0
T5	8877	0	0	0
T6	3148	0	0	0
T7	6260	0	0	0
T8	3623	0	0	0
T9	1013	0	0	0
T10	61746	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	10	0	0
T14	0	54	0	0
T23	0	6	0	0
T24	0	5	0	0
T31	0	15	0	0
T34	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21542849	860874	0	0
T1	6489	679	0	0
T2	855	17	0	0
T3	6142	0	0	0
T4	828	0	0	0
T5	8877	0	0	0
T6	3148	0	0	0
T7	6260	0	0	0
T8	3623	27	0	0
T9	1013	10	0	0
T10	61746	757	0	0
T14	0	9295	0	0
T20	0	887	0	0
T23	0	38	0	0
T28	0	22	0	0
T126	0	22	0	0