| T801 |
/workspace/coverage/default/6.pwrmgr_reset.4096342063 |
|
|
Mar 31 01:53:38 PM PDT 24 |
Mar 31 01:53:38 PM PDT 24 |
41786122 ps |
| T802 |
/workspace/coverage/default/4.pwrmgr_lowpower_wakeup_race.2251655564 |
|
|
Mar 31 01:53:20 PM PDT 24 |
Mar 31 01:53:21 PM PDT 24 |
172841835 ps |
| T803 |
/workspace/coverage/default/4.pwrmgr_reset.472247171 |
|
|
Mar 31 01:53:20 PM PDT 24 |
Mar 31 01:53:21 PM PDT 24 |
36428079 ps |
| T804 |
/workspace/coverage/default/43.pwrmgr_lowpower_invalid.3208420553 |
|
|
Mar 31 01:56:12 PM PDT 24 |
Mar 31 01:56:13 PM PDT 24 |
76230554 ps |
| T805 |
/workspace/coverage/default/15.pwrmgr_reset.3101111113 |
|
|
Mar 31 01:54:13 PM PDT 24 |
Mar 31 01:54:15 PM PDT 24 |
329358512 ps |
| T806 |
/workspace/coverage/default/14.pwrmgr_reset_invalid.2560524510 |
|
|
Mar 31 01:54:12 PM PDT 24 |
Mar 31 01:54:13 PM PDT 24 |
416526488 ps |
| T807 |
/workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.1326103138 |
|
|
Mar 31 01:53:08 PM PDT 24 |
Mar 31 01:53:10 PM PDT 24 |
87422400 ps |
| T808 |
/workspace/coverage/default/35.pwrmgr_reset.604536180 |
|
|
Mar 31 01:55:34 PM PDT 24 |
Mar 31 01:55:35 PM PDT 24 |
40513626 ps |
| T809 |
/workspace/coverage/default/14.pwrmgr_aborted_low_power.2700731921 |
|
|
Mar 31 01:54:05 PM PDT 24 |
Mar 31 01:54:06 PM PDT 24 |
20995493 ps |
| T810 |
/workspace/coverage/default/8.pwrmgr_reset_invalid.776636317 |
|
|
Mar 31 01:53:41 PM PDT 24 |
Mar 31 01:53:42 PM PDT 24 |
228349551 ps |
| T811 |
/workspace/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.721260441 |
|
|
Mar 31 01:55:52 PM PDT 24 |
Mar 31 01:55:54 PM PDT 24 |
1763003193 ps |
| T812 |
/workspace/coverage/default/27.pwrmgr_stress_all.3695810998 |
|
|
Mar 31 01:55:09 PM PDT 24 |
Mar 31 01:55:13 PM PDT 24 |
1702530671 ps |
| T813 |
/workspace/coverage/default/7.pwrmgr_global_esc.4260862256 |
|
|
Mar 31 01:53:41 PM PDT 24 |
Mar 31 01:53:42 PM PDT 24 |
86873468 ps |
| T814 |
/workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.2878267060 |
|
|
Mar 31 01:54:59 PM PDT 24 |
Mar 31 01:55:00 PM PDT 24 |
58547404 ps |
| T815 |
/workspace/coverage/default/3.pwrmgr_stress_all.3707527680 |
|
|
Mar 31 01:53:21 PM PDT 24 |
Mar 31 01:53:21 PM PDT 24 |
86045316 ps |
| T816 |
/workspace/coverage/default/37.pwrmgr_stress_all.710008346 |
|
|
Mar 31 01:55:47 PM PDT 24 |
Mar 31 01:55:51 PM PDT 24 |
3478378237 ps |
| T817 |
/workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.1289458112 |
|
|
Mar 31 01:56:16 PM PDT 24 |
Mar 31 01:56:17 PM PDT 24 |
118578704 ps |
| T818 |
/workspace/coverage/default/30.pwrmgr_aborted_low_power.1986567959 |
|
|
Mar 31 01:55:22 PM PDT 24 |
Mar 31 01:55:23 PM PDT 24 |
43508368 ps |
| T819 |
/workspace/coverage/default/11.pwrmgr_reset_invalid.444570338 |
|
|
Mar 31 01:54:06 PM PDT 24 |
Mar 31 01:54:07 PM PDT 24 |
165937175 ps |
| T820 |
/workspace/coverage/default/48.pwrmgr_reset.5795865 |
|
|
Mar 31 01:56:25 PM PDT 24 |
Mar 31 01:56:26 PM PDT 24 |
45142916 ps |
| T821 |
/workspace/coverage/default/45.pwrmgr_wakeup.3859416677 |
|
|
Mar 31 01:56:11 PM PDT 24 |
Mar 31 01:56:12 PM PDT 24 |
266499674 ps |
| T822 |
/workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.3712876125 |
|
|
Mar 31 01:56:20 PM PDT 24 |
Mar 31 01:56:21 PM PDT 24 |
48032375 ps |
| T823 |
/workspace/coverage/default/13.pwrmgr_reset.4124850027 |
|
|
Mar 31 01:54:01 PM PDT 24 |
Mar 31 01:54:02 PM PDT 24 |
53762453 ps |
| T824 |
/workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.1861568356 |
|
|
Mar 31 01:56:07 PM PDT 24 |
Mar 31 01:56:08 PM PDT 24 |
70590044 ps |
| T825 |
/workspace/coverage/default/39.pwrmgr_reset.2893842197 |
|
|
Mar 31 01:55:50 PM PDT 24 |
Mar 31 01:55:51 PM PDT 24 |
53995837 ps |
| T826 |
/workspace/coverage/default/17.pwrmgr_aborted_low_power.1417787757 |
|
|
Mar 31 01:54:21 PM PDT 24 |
Mar 31 01:54:22 PM PDT 24 |
50543804 ps |
| T827 |
/workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.4165199510 |
|
|
Mar 31 01:55:58 PM PDT 24 |
Mar 31 01:55:59 PM PDT 24 |
29637825 ps |
| T828 |
/workspace/coverage/default/26.pwrmgr_reset.3787352791 |
|
|
Mar 31 01:55:01 PM PDT 24 |
Mar 31 01:55:02 PM PDT 24 |
44066828 ps |
| T829 |
/workspace/coverage/default/12.pwrmgr_escalation_timeout.3316790933 |
|
|
Mar 31 01:54:02 PM PDT 24 |
Mar 31 01:54:03 PM PDT 24 |
165411846 ps |
| T830 |
/workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.1373167311 |
|
|
Mar 31 01:54:22 PM PDT 24 |
Mar 31 01:54:23 PM PDT 24 |
33065623 ps |
| T831 |
/workspace/coverage/default/29.pwrmgr_aborted_low_power.3583412867 |
|
|
Mar 31 01:55:30 PM PDT 24 |
Mar 31 01:55:31 PM PDT 24 |
70884949 ps |
| T832 |
/workspace/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1515472920 |
|
|
Mar 31 01:54:01 PM PDT 24 |
Mar 31 01:54:03 PM PDT 24 |
1083901434 ps |
| T833 |
/workspace/coverage/default/29.pwrmgr_lowpower_invalid.3929328205 |
|
|
Mar 31 01:55:18 PM PDT 24 |
Mar 31 01:55:19 PM PDT 24 |
44447423 ps |
| T834 |
/workspace/coverage/default/5.pwrmgr_lowpower_invalid.2241525675 |
|
|
Mar 31 01:53:25 PM PDT 24 |
Mar 31 01:53:26 PM PDT 24 |
43797777 ps |
| T835 |
/workspace/coverage/default/11.pwrmgr_reset.1466734548 |
|
|
Mar 31 01:53:54 PM PDT 24 |
Mar 31 01:53:55 PM PDT 24 |
117550881 ps |
| T836 |
/workspace/coverage/default/30.pwrmgr_lowpower_invalid.539173798 |
|
|
Mar 31 01:55:21 PM PDT 24 |
Mar 31 01:55:22 PM PDT 24 |
41702587 ps |
| T837 |
/workspace/coverage/default/32.pwrmgr_escalation_timeout.2012975794 |
|
|
Mar 31 01:55:29 PM PDT 24 |
Mar 31 01:55:31 PM PDT 24 |
210575023 ps |
| T838 |
/workspace/coverage/default/34.pwrmgr_lowpower_wakeup_race.716318687 |
|
|
Mar 31 01:55:32 PM PDT 24 |
Mar 31 01:55:33 PM PDT 24 |
88471546 ps |
| T839 |
/workspace/coverage/default/40.pwrmgr_aborted_low_power.4088854239 |
|
|
Mar 31 01:56:03 PM PDT 24 |
Mar 31 01:56:04 PM PDT 24 |
43982928 ps |
| T840 |
/workspace/coverage/default/6.pwrmgr_stress_all.3909638925 |
|
|
Mar 31 01:53:32 PM PDT 24 |
Mar 31 01:53:37 PM PDT 24 |
1344868514 ps |
| T841 |
/workspace/coverage/default/14.pwrmgr_reset.2928146612 |
|
|
Mar 31 01:54:04 PM PDT 24 |
Mar 31 01:54:05 PM PDT 24 |
88277671 ps |
| T842 |
/workspace/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2405339362 |
|
|
Mar 31 01:54:42 PM PDT 24 |
Mar 31 01:54:45 PM PDT 24 |
1249980262 ps |
| T843 |
/workspace/coverage/default/48.pwrmgr_smoke.3116041774 |
|
|
Mar 31 01:56:26 PM PDT 24 |
Mar 31 01:56:27 PM PDT 24 |
27419236 ps |
| T844 |
/workspace/coverage/default/34.pwrmgr_reset_invalid.482234773 |
|
|
Mar 31 01:55:36 PM PDT 24 |
Mar 31 01:55:37 PM PDT 24 |
112577010 ps |
| T845 |
/workspace/coverage/default/33.pwrmgr_stress_all_with_rand_reset.3407073048 |
|
|
Mar 31 01:55:36 PM PDT 24 |
Mar 31 01:55:58 PM PDT 24 |
6966971221 ps |
| T846 |
/workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.3391839592 |
|
|
Mar 31 01:53:40 PM PDT 24 |
Mar 31 01:53:41 PM PDT 24 |
182249234 ps |
| T847 |
/workspace/coverage/default/23.pwrmgr_wakeup.2901180212 |
|
|
Mar 31 01:54:52 PM PDT 24 |
Mar 31 01:54:53 PM PDT 24 |
290390347 ps |
| T848 |
/workspace/coverage/default/4.pwrmgr_wakeup.573478226 |
|
|
Mar 31 01:53:21 PM PDT 24 |
Mar 31 01:53:22 PM PDT 24 |
377001590 ps |
| T175 |
/workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.2059009554 |
|
|
Mar 31 01:54:01 PM PDT 24 |
Mar 31 01:54:02 PM PDT 24 |
57651734 ps |
| T849 |
/workspace/coverage/default/3.pwrmgr_global_esc.251891785 |
|
|
Mar 31 01:53:22 PM PDT 24 |
Mar 31 01:53:23 PM PDT 24 |
42768077 ps |
| T850 |
/workspace/coverage/default/47.pwrmgr_wakeup_reset.2808246864 |
|
|
Mar 31 01:56:23 PM PDT 24 |
Mar 31 01:56:24 PM PDT 24 |
640005298 ps |
| T851 |
/workspace/coverage/default/3.pwrmgr_reset.65914950 |
|
|
Mar 31 01:53:15 PM PDT 24 |
Mar 31 01:53:15 PM PDT 24 |
22807910 ps |
| T852 |
/workspace/coverage/default/24.pwrmgr_stress_all.891919798 |
|
|
Mar 31 01:54:55 PM PDT 24 |
Mar 31 01:54:59 PM PDT 24 |
923290249 ps |
| T853 |
/workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3789134867 |
|
|
Mar 31 01:53:31 PM PDT 24 |
Mar 31 01:53:32 PM PDT 24 |
65060882 ps |
| T854 |
/workspace/coverage/default/9.pwrmgr_aborted_low_power.2155303144 |
|
|
Mar 31 01:53:46 PM PDT 24 |
Mar 31 01:53:47 PM PDT 24 |
36667046 ps |
| T855 |
/workspace/coverage/default/39.pwrmgr_smoke.3788190649 |
|
|
Mar 31 01:55:50 PM PDT 24 |
Mar 31 01:55:51 PM PDT 24 |
39108697 ps |
| T856 |
/workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.1507892801 |
|
|
Mar 31 01:54:51 PM PDT 24 |
Mar 31 01:54:51 PM PDT 24 |
87861776 ps |
| T857 |
/workspace/coverage/default/39.pwrmgr_aborted_low_power.985520111 |
|
|
Mar 31 01:55:51 PM PDT 24 |
Mar 31 01:55:53 PM PDT 24 |
58223211 ps |
| T858 |
/workspace/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2721533573 |
|
|
Mar 31 01:53:37 PM PDT 24 |
Mar 31 01:53:40 PM PDT 24 |
2148098257 ps |
| T859 |
/workspace/coverage/default/11.pwrmgr_stress_all.4071860449 |
|
|
Mar 31 01:54:03 PM PDT 24 |
Mar 31 01:54:10 PM PDT 24 |
2097394481 ps |
| T860 |
/workspace/coverage/default/5.pwrmgr_escalation_timeout.2170790777 |
|
|
Mar 31 01:53:25 PM PDT 24 |
Mar 31 01:53:26 PM PDT 24 |
323919382 ps |
| T861 |
/workspace/coverage/default/38.pwrmgr_escalation_timeout.1016072718 |
|
|
Mar 31 01:55:54 PM PDT 24 |
Mar 31 01:55:56 PM PDT 24 |
160654108 ps |
| T862 |
/workspace/coverage/default/21.pwrmgr_escalation_timeout.2036825256 |
|
|
Mar 31 01:54:44 PM PDT 24 |
Mar 31 01:54:45 PM PDT 24 |
325947651 ps |
| T863 |
/workspace/coverage/default/1.pwrmgr_glitch.3651779336 |
|
|
Mar 31 01:53:07 PM PDT 24 |
Mar 31 01:53:08 PM PDT 24 |
52161449 ps |
| T864 |
/workspace/coverage/default/6.pwrmgr_reset_invalid.3967084715 |
|
|
Mar 31 01:53:32 PM PDT 24 |
Mar 31 01:53:33 PM PDT 24 |
98501136 ps |
| T865 |
/workspace/coverage/default/19.pwrmgr_lowpower_invalid.2454524834 |
|
|
Mar 31 01:54:41 PM PDT 24 |
Mar 31 01:54:42 PM PDT 24 |
45483844 ps |
| T866 |
/workspace/coverage/default/2.pwrmgr_lowpower_wakeup_race.2966298767 |
|
|
Mar 31 01:53:08 PM PDT 24 |
Mar 31 01:53:11 PM PDT 24 |
278544371 ps |
| T867 |
/workspace/coverage/default/2.pwrmgr_reset_invalid.3505952995 |
|
|
Mar 31 01:53:13 PM PDT 24 |
Mar 31 01:53:14 PM PDT 24 |
294815059 ps |
| T868 |
/workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.3527565482 |
|
|
Mar 31 01:55:25 PM PDT 24 |
Mar 31 01:55:26 PM PDT 24 |
71684514 ps |
| T869 |
/workspace/coverage/default/11.pwrmgr_smoke.3193478669 |
|
|
Mar 31 01:53:56 PM PDT 24 |
Mar 31 01:53:57 PM PDT 24 |
32803741 ps |
| T870 |
/workspace/coverage/default/43.pwrmgr_lowpower_wakeup_race.3628203399 |
|
|
Mar 31 01:56:04 PM PDT 24 |
Mar 31 01:56:05 PM PDT 24 |
283083010 ps |
| T871 |
/workspace/coverage/default/12.pwrmgr_glitch.2963580779 |
|
|
Mar 31 01:53:59 PM PDT 24 |
Mar 31 01:54:00 PM PDT 24 |
25595926 ps |
| T872 |
/workspace/coverage/default/24.pwrmgr_smoke.488542816 |
|
|
Mar 31 01:54:48 PM PDT 24 |
Mar 31 01:54:49 PM PDT 24 |
212793701 ps |
| T873 |
/workspace/coverage/default/20.pwrmgr_global_esc.3371164906 |
|
|
Mar 31 01:54:39 PM PDT 24 |
Mar 31 01:54:40 PM PDT 24 |
56363523 ps |
| T874 |
/workspace/coverage/default/46.pwrmgr_smoke.468901086 |
|
|
Mar 31 01:56:15 PM PDT 24 |
Mar 31 01:56:16 PM PDT 24 |
26914542 ps |
| T875 |
/workspace/coverage/default/46.pwrmgr_reset_invalid.2536937860 |
|
|
Mar 31 01:56:19 PM PDT 24 |
Mar 31 01:56:19 PM PDT 24 |
112171106 ps |
| T876 |
/workspace/coverage/default/10.pwrmgr_global_esc.107753510 |
|
|
Mar 31 01:53:54 PM PDT 24 |
Mar 31 01:53:54 PM PDT 24 |
82581433 ps |
| T877 |
/workspace/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.574456646 |
|
|
Mar 31 01:54:22 PM PDT 24 |
Mar 31 01:54:25 PM PDT 24 |
1451583559 ps |
| T878 |
/workspace/coverage/default/1.pwrmgr_reset.237678237 |
|
|
Mar 31 01:53:02 PM PDT 24 |
Mar 31 01:53:04 PM PDT 24 |
46546893 ps |
| T879 |
/workspace/coverage/default/25.pwrmgr_stress_all.1861307373 |
|
|
Mar 31 01:54:59 PM PDT 24 |
Mar 31 01:55:03 PM PDT 24 |
2770109262 ps |
| T880 |
/workspace/coverage/default/29.pwrmgr_smoke.166973629 |
|
|
Mar 31 01:55:13 PM PDT 24 |
Mar 31 01:55:13 PM PDT 24 |
221571220 ps |
| T881 |
/workspace/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.187887221 |
|
|
Mar 31 01:54:51 PM PDT 24 |
Mar 31 01:54:53 PM PDT 24 |
163351785 ps |
| T882 |
/workspace/coverage/default/17.pwrmgr_wakeup_reset.3108970496 |
|
|
Mar 31 01:54:20 PM PDT 24 |
Mar 31 01:54:22 PM PDT 24 |
196200558 ps |
| T883 |
/workspace/coverage/default/26.pwrmgr_reset_invalid.1635258021 |
|
|
Mar 31 01:55:04 PM PDT 24 |
Mar 31 01:55:05 PM PDT 24 |
189996355 ps |
| T884 |
/workspace/coverage/default/9.pwrmgr_lowpower_wakeup_race.2761450140 |
|
|
Mar 31 01:53:46 PM PDT 24 |
Mar 31 01:53:47 PM PDT 24 |
150296012 ps |
| T885 |
/workspace/coverage/default/12.pwrmgr_smoke.1766712289 |
|
|
Mar 31 01:53:59 PM PDT 24 |
Mar 31 01:54:00 PM PDT 24 |
34261829 ps |
| T886 |
/workspace/coverage/default/27.pwrmgr_reset.1155434785 |
|
|
Mar 31 01:55:03 PM PDT 24 |
Mar 31 01:55:03 PM PDT 24 |
104749727 ps |
| T887 |
/workspace/coverage/default/43.pwrmgr_wakeup_reset.4191587312 |
|
|
Mar 31 01:56:05 PM PDT 24 |
Mar 31 01:56:07 PM PDT 24 |
270054112 ps |
| T888 |
/workspace/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.1794426925 |
|
|
Mar 31 01:53:21 PM PDT 24 |
Mar 31 01:53:22 PM PDT 24 |
110100649 ps |
| T889 |
/workspace/coverage/default/5.pwrmgr_wakeup_reset.2479537005 |
|
|
Mar 31 01:53:28 PM PDT 24 |
Mar 31 01:53:29 PM PDT 24 |
48067704 ps |
| T890 |
/workspace/coverage/default/41.pwrmgr_reset.133180797 |
|
|
Mar 31 01:56:03 PM PDT 24 |
Mar 31 01:56:04 PM PDT 24 |
49258719 ps |
| T891 |
/workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.188641075 |
|
|
Mar 31 01:54:00 PM PDT 24 |
Mar 31 01:54:01 PM PDT 24 |
162467742 ps |
| T892 |
/workspace/coverage/default/42.pwrmgr_wakeup_reset.3575173443 |
|
|
Mar 31 01:56:06 PM PDT 24 |
Mar 31 01:56:07 PM PDT 24 |
199219514 ps |
| T893 |
/workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.2261803512 |
|
|
Mar 31 01:54:28 PM PDT 24 |
Mar 31 01:54:29 PM PDT 24 |
394799599 ps |
| T894 |
/workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.3476177993 |
|
|
Mar 31 01:53:22 PM PDT 24 |
Mar 31 01:53:23 PM PDT 24 |
40199947 ps |
| T895 |
/workspace/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1016204530 |
|
|
Mar 31 01:55:26 PM PDT 24 |
Mar 31 01:55:28 PM PDT 24 |
3659115242 ps |
| T896 |
/workspace/coverage/default/6.pwrmgr_lowpower_invalid.392416704 |
|
|
Mar 31 01:53:31 PM PDT 24 |
Mar 31 01:53:32 PM PDT 24 |
56530323 ps |
| T897 |
/workspace/coverage/default/8.pwrmgr_smoke.2446529574 |
|
|
Mar 31 01:53:42 PM PDT 24 |
Mar 31 01:53:43 PM PDT 24 |
28788369 ps |
| T898 |
/workspace/coverage/default/31.pwrmgr_wakeup.3297161688 |
|
|
Mar 31 01:55:19 PM PDT 24 |
Mar 31 01:55:20 PM PDT 24 |
309306250 ps |
| T899 |
/workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.3826986473 |
|
|
Mar 31 01:53:44 PM PDT 24 |
Mar 31 01:53:45 PM PDT 24 |
45114776 ps |
| T900 |
/workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.852165735 |
|
|
Mar 31 01:53:53 PM PDT 24 |
Mar 31 01:53:54 PM PDT 24 |
66084440 ps |
| T901 |
/workspace/coverage/default/24.pwrmgr_global_esc.3826285010 |
|
|
Mar 31 01:54:52 PM PDT 24 |
Mar 31 01:54:53 PM PDT 24 |
31295346 ps |
| T902 |
/workspace/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.480336295 |
|
|
Mar 31 01:54:06 PM PDT 24 |
Mar 31 01:54:09 PM PDT 24 |
859342652 ps |
| T903 |
/workspace/coverage/default/36.pwrmgr_reset.3484954915 |
|
|
Mar 31 01:55:41 PM PDT 24 |
Mar 31 01:55:43 PM PDT 24 |
191428052 ps |
| T904 |
/workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.463752802 |
|
|
Mar 31 01:54:07 PM PDT 24 |
Mar 31 01:54:08 PM PDT 24 |
31032164 ps |
| T905 |
/workspace/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2179037317 |
|
|
Mar 31 01:55:20 PM PDT 24 |
Mar 31 01:55:23 PM PDT 24 |
1817176751 ps |
| T906 |
/workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.3485717669 |
|
|
Mar 31 01:54:05 PM PDT 24 |
Mar 31 01:54:06 PM PDT 24 |
189764070 ps |
| T907 |
/workspace/coverage/default/18.pwrmgr_wakeup.2826640930 |
|
|
Mar 31 01:54:32 PM PDT 24 |
Mar 31 01:54:33 PM PDT 24 |
289952800 ps |
| T908 |
/workspace/coverage/default/23.pwrmgr_lowpower_wakeup_race.4167640690 |
|
|
Mar 31 01:54:46 PM PDT 24 |
Mar 31 01:54:47 PM PDT 24 |
308818839 ps |
| T909 |
/workspace/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3456954465 |
|
|
Mar 31 01:53:52 PM PDT 24 |
Mar 31 01:53:55 PM PDT 24 |
1106986003 ps |
| T910 |
/workspace/coverage/default/12.pwrmgr_lowpower_invalid.3116778061 |
|
|
Mar 31 01:54:00 PM PDT 24 |
Mar 31 01:54:01 PM PDT 24 |
45644927 ps |
| T911 |
/workspace/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.3994656453 |
|
|
Mar 31 01:54:39 PM PDT 24 |
Mar 31 01:54:40 PM PDT 24 |
266672674 ps |
| T912 |
/workspace/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.602464496 |
|
|
Mar 31 01:54:38 PM PDT 24 |
Mar 31 01:54:39 PM PDT 24 |
349565471 ps |
| T913 |
/workspace/coverage/default/30.pwrmgr_stress_all.4185477210 |
|
|
Mar 31 01:55:21 PM PDT 24 |
Mar 31 01:55:23 PM PDT 24 |
124485064 ps |
| T914 |
/workspace/coverage/default/8.pwrmgr_stress_all.4134627277 |
|
|
Mar 31 01:53:41 PM PDT 24 |
Mar 31 01:53:42 PM PDT 24 |
71770579 ps |
| T915 |
/workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.2497923955 |
|
|
Mar 31 01:54:00 PM PDT 24 |
Mar 31 01:54:01 PM PDT 24 |
98663508 ps |
| T916 |
/workspace/coverage/default/28.pwrmgr_stress_all_with_rand_reset.2625776003 |
|
|
Mar 31 01:55:13 PM PDT 24 |
Mar 31 01:55:24 PM PDT 24 |
6171842880 ps |
| T917 |
/workspace/coverage/default/38.pwrmgr_smoke.1382098736 |
|
|
Mar 31 01:55:45 PM PDT 24 |
Mar 31 01:55:46 PM PDT 24 |
30348920 ps |
| T918 |
/workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.526460931 |
|
|
Mar 31 01:56:30 PM PDT 24 |
Mar 31 01:56:31 PM PDT 24 |
210414304 ps |
| T919 |
/workspace/coverage/default/8.pwrmgr_lowpower_wakeup_race.32261482 |
|
|
Mar 31 01:53:45 PM PDT 24 |
Mar 31 01:53:46 PM PDT 24 |
408167773 ps |
| T920 |
/workspace/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.401305337 |
|
|
Mar 31 01:56:35 PM PDT 24 |
Mar 31 01:56:35 PM PDT 24 |
152427548 ps |
| T921 |
/workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.2162177225 |
|
|
Mar 31 01:55:07 PM PDT 24 |
Mar 31 01:55:08 PM PDT 24 |
51698965 ps |
| T922 |
/workspace/coverage/default/2.pwrmgr_stress_all.2784226760 |
|
|
Mar 31 01:53:13 PM PDT 24 |
Mar 31 01:53:18 PM PDT 24 |
1088188169 ps |
| T923 |
/workspace/coverage/default/42.pwrmgr_lowpower_invalid.665451033 |
|
|
Mar 31 01:56:05 PM PDT 24 |
Mar 31 01:56:06 PM PDT 24 |
47900222 ps |
| T924 |
/workspace/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.541438872 |
|
|
Mar 31 01:52:55 PM PDT 24 |
Mar 31 01:52:57 PM PDT 24 |
936256970 ps |
| T925 |
/workspace/coverage/default/49.pwrmgr_wakeup.1991669063 |
|
|
Mar 31 01:56:36 PM PDT 24 |
Mar 31 01:56:37 PM PDT 24 |
228703510 ps |
| T926 |
/workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.2914611881 |
|
|
Mar 31 01:56:24 PM PDT 24 |
Mar 31 01:56:25 PM PDT 24 |
54855026 ps |
| T927 |
/workspace/coverage/default/41.pwrmgr_lowpower_wakeup_race.4184676028 |
|
|
Mar 31 01:56:01 PM PDT 24 |
Mar 31 01:56:02 PM PDT 24 |
246533511 ps |
| T928 |
/workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.4190254677 |
|
|
Mar 31 01:55:15 PM PDT 24 |
Mar 31 01:55:16 PM PDT 24 |
112577530 ps |
| T929 |
/workspace/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1305509572 |
|
|
Mar 31 01:55:07 PM PDT 24 |
Mar 31 01:55:10 PM PDT 24 |
828250385 ps |
| T930 |
/workspace/coverage/default/46.pwrmgr_lowpower_invalid.3003865849 |
|
|
Mar 31 01:56:20 PM PDT 24 |
Mar 31 01:56:20 PM PDT 24 |
172940821 ps |
| T931 |
/workspace/coverage/default/35.pwrmgr_aborted_low_power.2891800380 |
|
|
Mar 31 01:55:33 PM PDT 24 |
Mar 31 01:55:34 PM PDT 24 |
74233331 ps |
| T932 |
/workspace/coverage/default/28.pwrmgr_lowpower_invalid.2190619669 |
|
|
Mar 31 01:55:18 PM PDT 24 |
Mar 31 01:55:18 PM PDT 24 |
81100978 ps |
| T933 |
/workspace/coverage/default/5.pwrmgr_stress_all.38995445 |
|
|
Mar 31 01:53:31 PM PDT 24 |
Mar 31 01:53:36 PM PDT 24 |
1480842274 ps |
| T97 |
/workspace/coverage/default/36.pwrmgr_stress_all_with_rand_reset.1901467198 |
|
|
Mar 31 01:55:44 PM PDT 24 |
Mar 31 01:56:03 PM PDT 24 |
8181824187 ps |
| T934 |
/workspace/coverage/default/25.pwrmgr_wakeup_reset.1194814634 |
|
|
Mar 31 01:54:57 PM PDT 24 |
Mar 31 01:54:58 PM PDT 24 |
223555590 ps |
| T935 |
/workspace/coverage/default/6.pwrmgr_wakeup_reset.4065506446 |
|
|
Mar 31 01:53:34 PM PDT 24 |
Mar 31 01:53:35 PM PDT 24 |
147341932 ps |
| T936 |
/workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.400984610 |
|
|
Mar 31 01:55:37 PM PDT 24 |
Mar 31 01:55:38 PM PDT 24 |
184858111 ps |
| T937 |
/workspace/coverage/default/1.pwrmgr_stress_all_with_rand_reset.3484697357 |
|
|
Mar 31 01:53:11 PM PDT 24 |
Mar 31 01:53:15 PM PDT 24 |
2575679616 ps |
| T938 |
/workspace/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.532330067 |
|
|
Mar 31 01:53:54 PM PDT 24 |
Mar 31 01:53:55 PM PDT 24 |
310799209 ps |
| T939 |
/workspace/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4030052908 |
|
|
Mar 31 01:53:42 PM PDT 24 |
Mar 31 01:53:44 PM PDT 24 |
800550915 ps |
| T940 |
/workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.3054705529 |
|
|
Mar 31 01:56:14 PM PDT 24 |
Mar 31 01:56:15 PM PDT 24 |
64515048 ps |
| T941 |
/workspace/coverage/default/3.pwrmgr_lowpower_invalid.1274643650 |
|
|
Mar 31 01:53:24 PM PDT 24 |
Mar 31 01:53:25 PM PDT 24 |
66540665 ps |
| T942 |
/workspace/coverage/default/19.pwrmgr_glitch.2900221236 |
|
|
Mar 31 01:54:36 PM PDT 24 |
Mar 31 01:54:37 PM PDT 24 |
24028759 ps |
| T943 |
/workspace/coverage/default/25.pwrmgr_glitch.2386706424 |
|
|
Mar 31 01:54:56 PM PDT 24 |
Mar 31 01:54:56 PM PDT 24 |
105916556 ps |
| T944 |
/workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.3435984455 |
|
|
Mar 31 01:53:31 PM PDT 24 |
Mar 31 01:53:32 PM PDT 24 |
49775515 ps |
| T945 |
/workspace/coverage/default/14.pwrmgr_stress_all.3543261809 |
|
|
Mar 31 01:54:15 PM PDT 24 |
Mar 31 01:54:19 PM PDT 24 |
600857541 ps |
| T946 |
/workspace/coverage/default/21.pwrmgr_lowpower_wakeup_race.1382931315 |
|
|
Mar 31 01:54:39 PM PDT 24 |
Mar 31 01:54:40 PM PDT 24 |
178386186 ps |
| T947 |
/workspace/coverage/default/45.pwrmgr_stress_all_with_rand_reset.1790976880 |
|
|
Mar 31 01:56:18 PM PDT 24 |
Mar 31 01:56:25 PM PDT 24 |
6034725360 ps |
| T948 |
/workspace/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.1487460523 |
|
|
Mar 31 01:55:06 PM PDT 24 |
Mar 31 01:55:08 PM PDT 24 |
202805546 ps |
| T949 |
/workspace/coverage/default/40.pwrmgr_wakeup.693054816 |
|
|
Mar 31 01:55:57 PM PDT 24 |
Mar 31 01:55:58 PM PDT 24 |
91901053 ps |
| T950 |
/workspace/coverage/default/10.pwrmgr_glitch.1945116110 |
|
|
Mar 31 01:53:55 PM PDT 24 |
Mar 31 01:53:56 PM PDT 24 |
52861373 ps |
| T951 |
/workspace/coverage/default/25.pwrmgr_escalation_timeout.1608464204 |
|
|
Mar 31 01:54:57 PM PDT 24 |
Mar 31 01:54:58 PM PDT 24 |
691628588 ps |
| T952 |
/workspace/coverage/default/39.pwrmgr_global_esc.1174855260 |
|
|
Mar 31 01:55:54 PM PDT 24 |
Mar 31 01:55:55 PM PDT 24 |
47289741 ps |
| T953 |
/workspace/coverage/default/4.pwrmgr_global_esc.1464546726 |
|
|
Mar 31 01:53:25 PM PDT 24 |
Mar 31 01:53:25 PM PDT 24 |
36336669 ps |
| T954 |
/workspace/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2344354382 |
|
|
Mar 31 01:56:19 PM PDT 24 |
Mar 31 01:56:21 PM PDT 24 |
818375159 ps |
| T955 |
/workspace/coverage/default/11.pwrmgr_escalation_timeout.2830541518 |
|
|
Mar 31 01:54:00 PM PDT 24 |
Mar 31 01:54:01 PM PDT 24 |
610810556 ps |
| T956 |
/workspace/coverage/default/10.pwrmgr_lowpower_wakeup_race.731419163 |
|
|
Mar 31 01:53:45 PM PDT 24 |
Mar 31 01:53:46 PM PDT 24 |
253088541 ps |
| T957 |
/workspace/coverage/default/19.pwrmgr_lowpower_wakeup_race.2526758598 |
|
|
Mar 31 01:54:36 PM PDT 24 |
Mar 31 01:54:38 PM PDT 24 |
220554730 ps |
| T958 |
/workspace/coverage/default/41.pwrmgr_aborted_low_power.4031519665 |
|
|
Mar 31 01:56:05 PM PDT 24 |
Mar 31 01:56:06 PM PDT 24 |
205237142 ps |
| T959 |
/workspace/coverage/default/10.pwrmgr_lowpower_invalid.2227992535 |
|
|
Mar 31 01:53:52 PM PDT 24 |
Mar 31 01:53:53 PM PDT 24 |
40945754 ps |
| T960 |
/workspace/coverage/default/49.pwrmgr_reset_invalid.2344986222 |
|
|
Mar 31 01:56:34 PM PDT 24 |
Mar 31 01:56:35 PM PDT 24 |
211213599 ps |
| T961 |
/workspace/coverage/default/38.pwrmgr_reset.1850720472 |
|
|
Mar 31 01:55:47 PM PDT 24 |
Mar 31 01:55:48 PM PDT 24 |
53096863 ps |
| T962 |
/workspace/coverage/default/47.pwrmgr_global_esc.2875280222 |
|
|
Mar 31 01:56:24 PM PDT 24 |
Mar 31 01:56:25 PM PDT 24 |
23364002 ps |
| T963 |
/workspace/coverage/default/0.pwrmgr_aborted_low_power.224563260 |
|
|
Mar 31 01:52:58 PM PDT 24 |
Mar 31 01:53:00 PM PDT 24 |
38859534 ps |
| T964 |
/workspace/coverage/default/29.pwrmgr_global_esc.3885574920 |
|
|
Mar 31 01:55:14 PM PDT 24 |
Mar 31 01:55:14 PM PDT 24 |
43347413 ps |
| T965 |
/workspace/coverage/default/15.pwrmgr_lowpower_invalid.425735267 |
|
|
Mar 31 01:54:20 PM PDT 24 |
Mar 31 01:54:22 PM PDT 24 |
42408415 ps |
| T966 |
/workspace/coverage/default/39.pwrmgr_wakeup_reset.1935949508 |
|
|
Mar 31 01:55:56 PM PDT 24 |
Mar 31 01:55:58 PM PDT 24 |
215573330 ps |
| T967 |
/workspace/coverage/default/35.pwrmgr_escalation_timeout.3173497163 |
|
|
Mar 31 01:55:37 PM PDT 24 |
Mar 31 01:55:38 PM PDT 24 |
616535314 ps |
| T968 |
/workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.2587427567 |
|
|
Mar 31 01:55:20 PM PDT 24 |
Mar 31 01:55:21 PM PDT 24 |
65439301 ps |
| T969 |
/workspace/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2243732596 |
|
|
Mar 31 01:55:01 PM PDT 24 |
Mar 31 01:55:04 PM PDT 24 |
836670301 ps |
| T970 |
/workspace/coverage/default/43.pwrmgr_aborted_low_power.107770974 |
|
|
Mar 31 01:56:05 PM PDT 24 |
Mar 31 01:56:06 PM PDT 24 |
40234256 ps |
| T971 |
/workspace/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.2392863078 |
|
|
Mar 31 01:54:18 PM PDT 24 |
Mar 31 01:54:19 PM PDT 24 |
186550828 ps |
| T972 |
/workspace/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.2306109051 |
|
|
Mar 31 01:56:13 PM PDT 24 |
Mar 31 01:56:14 PM PDT 24 |
45703042 ps |
| T973 |
/workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.2655307058 |
|
|
Mar 31 01:56:26 PM PDT 24 |
Mar 31 01:56:27 PM PDT 24 |
28292860 ps |
| T974 |
/workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.853144572 |
|
|
Mar 31 01:56:14 PM PDT 24 |
Mar 31 01:56:15 PM PDT 24 |
67055065 ps |
| T975 |
/workspace/coverage/default/9.pwrmgr_escalation_timeout.695983100 |
|
|
Mar 31 01:53:50 PM PDT 24 |
Mar 31 01:53:51 PM PDT 24 |
333027050 ps |
| T976 |
/workspace/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.1039108738 |
|
|
Mar 31 01:54:43 PM PDT 24 |
Mar 31 01:54:44 PM PDT 24 |
97785329 ps |
| T977 |
/workspace/coverage/default/21.pwrmgr_aborted_low_power.1332862166 |
|
|
Mar 31 01:54:48 PM PDT 24 |
Mar 31 01:54:49 PM PDT 24 |
57985907 ps |
| T978 |
/workspace/coverage/default/41.pwrmgr_wakeup.1227627360 |
|
|
Mar 31 01:55:56 PM PDT 24 |
Mar 31 01:55:57 PM PDT 24 |
125634843 ps |
| T979 |
/workspace/coverage/default/19.pwrmgr_escalation_timeout.88554868 |
|
|
Mar 31 01:54:38 PM PDT 24 |
Mar 31 01:54:39 PM PDT 24 |
202469610 ps |
| T980 |
/workspace/coverage/default/34.pwrmgr_escalation_timeout.3171467126 |
|
|
Mar 31 01:55:35 PM PDT 24 |
Mar 31 01:55:36 PM PDT 24 |
159187498 ps |
| T981 |
/workspace/coverage/default/39.pwrmgr_wakeup.1886080816 |
|
|
Mar 31 01:55:52 PM PDT 24 |
Mar 31 01:55:53 PM PDT 24 |
168808980 ps |
| T982 |
/workspace/coverage/default/42.pwrmgr_reset_invalid.536573111 |
|
|
Mar 31 01:56:08 PM PDT 24 |
Mar 31 01:56:09 PM PDT 24 |
148852057 ps |
| T983 |
/workspace/coverage/default/32.pwrmgr_lowpower_invalid.4162029429 |
|
|
Mar 31 01:55:28 PM PDT 24 |
Mar 31 01:55:29 PM PDT 24 |
106806234 ps |
| T984 |
/workspace/coverage/default/13.pwrmgr_escalation_timeout.1752682772 |
|
|
Mar 31 01:54:10 PM PDT 24 |
Mar 31 01:54:12 PM PDT 24 |
158706938 ps |
| T985 |
/workspace/coverage/default/47.pwrmgr_lowpower_invalid.1314457544 |
|
|
Mar 31 01:56:24 PM PDT 24 |
Mar 31 01:56:25 PM PDT 24 |
50560881 ps |
| T986 |
/workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.3308757330 |
|
|
Mar 31 01:54:59 PM PDT 24 |
Mar 31 01:55:00 PM PDT 24 |
131709166 ps |
| T987 |
/workspace/coverage/default/35.pwrmgr_glitch.4098394962 |
|
|
Mar 31 01:55:40 PM PDT 24 |
Mar 31 01:55:41 PM PDT 24 |
60204857 ps |
| T988 |
/workspace/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.307787088 |
|
|
Mar 31 01:55:28 PM PDT 24 |
Mar 31 01:55:31 PM PDT 24 |
811950892 ps |
| T989 |
/workspace/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.87032539 |
|
|
Mar 31 01:54:53 PM PDT 24 |
Mar 31 01:54:55 PM PDT 24 |
1115178002 ps |
| T990 |
/workspace/coverage/default/44.pwrmgr_reset.2300236797 |
|
|
Mar 31 01:56:17 PM PDT 24 |
Mar 31 01:56:18 PM PDT 24 |
88567262 ps |
| T991 |
/workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.70766962 |
|
|
Mar 31 01:54:05 PM PDT 24 |
Mar 31 01:54:06 PM PDT 24 |
176770915 ps |
| T992 |
/workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.1059438931 |
|
|
Mar 31 01:53:52 PM PDT 24 |
Mar 31 01:53:53 PM PDT 24 |
64792718 ps |
| T70 |
/workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.492934041 |
|
|
Mar 31 12:25:09 PM PDT 24 |
Mar 31 12:25:10 PM PDT 24 |
75728938 ps |
| T66 |
/workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.256824943 |
|
|
Mar 31 12:25:20 PM PDT 24 |
Mar 31 12:25:21 PM PDT 24 |
27161654 ps |
| T67 |
/workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.627101539 |
|
|
Mar 31 12:25:12 PM PDT 24 |
Mar 31 12:25:13 PM PDT 24 |
135592956 ps |
| T68 |
/workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.431188892 |
|
|
Mar 31 12:25:14 PM PDT 24 |
Mar 31 12:25:15 PM PDT 24 |
18085015 ps |
| T166 |
/workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.2328015932 |
|
|
Mar 31 12:25:37 PM PDT 24 |
Mar 31 12:25:38 PM PDT 24 |
59408004 ps |
| T167 |
/workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.2736110649 |
|
|
Mar 31 12:25:23 PM PDT 24 |
Mar 31 12:25:23 PM PDT 24 |
17158157 ps |
| T168 |
/workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.680968461 |
|
|
Mar 31 12:25:40 PM PDT 24 |
Mar 31 12:25:41 PM PDT 24 |
42088538 ps |
| T59 |
/workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2548976590 |
|
|
Mar 31 12:25:43 PM PDT 24 |
Mar 31 12:25:45 PM PDT 24 |
39675493 ps |
| T46 |
/workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.3089031702 |
|
|
Mar 31 12:25:47 PM PDT 24 |
Mar 31 12:25:49 PM PDT 24 |
30894003 ps |
| T119 |
/workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.278247104 |
|
|
Mar 31 12:25:05 PM PDT 24 |
Mar 31 12:25:06 PM PDT 24 |
39554119 ps |
| T56 |
/workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.1545490369 |
|
|
Mar 31 12:25:16 PM PDT 24 |
Mar 31 12:25:17 PM PDT 24 |
22951218 ps |
| T57 |
/workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1368210448 |
|
|
Mar 31 12:25:16 PM PDT 24 |
Mar 31 12:25:18 PM PDT 24 |
355975566 ps |
| T169 |
/workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.640031297 |
|
|
Mar 31 12:25:18 PM PDT 24 |
Mar 31 12:25:18 PM PDT 24 |
32879123 ps |
| T993 |
/workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.1473194194 |
|
|
Mar 31 12:25:10 PM PDT 24 |
Mar 31 12:25:11 PM PDT 24 |
55246923 ps |
| T58 |
/workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2611070778 |
|
|
Mar 31 12:25:40 PM PDT 24 |
Mar 31 12:25:42 PM PDT 24 |
58585396 ps |
| T120 |
/workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.907687216 |
|
|
Mar 31 12:25:28 PM PDT 24 |
Mar 31 12:25:29 PM PDT 24 |
49633846 ps |
| T121 |
/workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.716905386 |
|
|
Mar 31 12:25:07 PM PDT 24 |
Mar 31 12:25:08 PM PDT 24 |
26459239 ps |
| T49 |
/workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1913684622 |
|
|
Mar 31 12:25:19 PM PDT 24 |
Mar 31 12:25:20 PM PDT 24 |
104907108 ps |
| T106 |
/workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.873778772 |
|
|
Mar 31 12:25:55 PM PDT 24 |
Mar 31 12:25:56 PM PDT 24 |
20436821 ps |
| T51 |
/workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.2719140418 |
|
|
Mar 31 12:25:52 PM PDT 24 |
Mar 31 12:25:54 PM PDT 24 |
358738194 ps |
| T52 |
/workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2279876747 |
|
|
Mar 31 12:25:15 PM PDT 24 |
Mar 31 12:25:17 PM PDT 24 |
398075499 ps |
| T122 |
/workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1862302880 |
|
|
Mar 31 12:25:13 PM PDT 24 |
Mar 31 12:25:14 PM PDT 24 |
28215056 ps |
| T123 |
/workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2519669238 |
|
|
Mar 31 12:25:09 PM PDT 24 |
Mar 31 12:25:10 PM PDT 24 |
19180455 ps |
| T107 |
/workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.1184435743 |
|
|
Mar 31 12:26:43 PM PDT 24 |
Mar 31 12:26:44 PM PDT 24 |
43385493 ps |
| T994 |
/workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3625264638 |
|
|
Mar 31 12:25:14 PM PDT 24 |
Mar 31 12:25:15 PM PDT 24 |
49779283 ps |
| T995 |
/workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.2588951806 |
|
|
Mar 31 12:25:51 PM PDT 24 |
Mar 31 12:25:52 PM PDT 24 |
60620880 ps |
| T73 |
/workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.1076247251 |
|
|
Mar 31 12:25:47 PM PDT 24 |
Mar 31 12:25:47 PM PDT 24 |
40556361 ps |
| T53 |
/workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2052926805 |
|
|
Mar 31 12:25:11 PM PDT 24 |
Mar 31 12:25:12 PM PDT 24 |
146507801 ps |
| T69 |
/workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1980206653 |
|
|
Mar 31 12:25:07 PM PDT 24 |
Mar 31 12:25:09 PM PDT 24 |
197035147 ps |
| T996 |
/workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.533556643 |
|
|
Mar 31 12:25:14 PM PDT 24 |
Mar 31 12:25:15 PM PDT 24 |
15824950 ps |
| T997 |
/workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.883741028 |
|
|
Mar 31 12:25:15 PM PDT 24 |
Mar 31 12:25:16 PM PDT 24 |
47841885 ps |
| T998 |
/workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3332115426 |
|
|
Mar 31 12:26:02 PM PDT 24 |
Mar 31 12:26:03 PM PDT 24 |
19960427 ps |
| T62 |
/workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.3881645976 |
|
|
Mar 31 12:25:10 PM PDT 24 |
Mar 31 12:25:12 PM PDT 24 |
1875314325 ps |
| T999 |
/workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.194306706 |
|
|
Mar 31 12:25:24 PM PDT 24 |
Mar 31 12:25:25 PM PDT 24 |
52791534 ps |
| T170 |
/workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.295942626 |
|
|
Mar 31 12:25:37 PM PDT 24 |
Mar 31 12:25:38 PM PDT 24 |
55194230 ps |
| T164 |
/workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3029649645 |
|
|
Mar 31 12:25:16 PM PDT 24 |
Mar 31 12:25:18 PM PDT 24 |
268675586 ps |
| T1000 |
/workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2378757525 |
|
|
Mar 31 12:25:40 PM PDT 24 |
Mar 31 12:25:41 PM PDT 24 |
28935621 ps |
| T1001 |
/workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.3440912622 |
|
|
Mar 31 12:25:48 PM PDT 24 |
Mar 31 12:25:48 PM PDT 24 |
17884462 ps |
| T63 |
/workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.3935552062 |
|
|
Mar 31 12:25:27 PM PDT 24 |
Mar 31 12:25:29 PM PDT 24 |
188883289 ps |
| T64 |
/workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.812876512 |
|
|
Mar 31 12:25:21 PM PDT 24 |
Mar 31 12:25:22 PM PDT 24 |
180928558 ps |
| T1002 |
/workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.950760972 |
|
|
Mar 31 12:25:19 PM PDT 24 |
Mar 31 12:25:20 PM PDT 24 |
65887940 ps |
| T108 |
/workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3699014624 |
|
|
Mar 31 12:25:15 PM PDT 24 |
Mar 31 12:25:16 PM PDT 24 |
66104918 ps |
| T1003 |
/workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3399292249 |
|
|
Mar 31 12:25:40 PM PDT 24 |
Mar 31 12:25:41 PM PDT 24 |
86823836 ps |
| T1004 |
/workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.1487096531 |
|
|
Mar 31 12:25:12 PM PDT 24 |
Mar 31 12:25:14 PM PDT 24 |
52545511 ps |
| T1005 |
/workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.149547722 |
|
|
Mar 31 12:25:26 PM PDT 24 |
Mar 31 12:25:27 PM PDT 24 |
74714321 ps |
| T1006 |
/workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.680354341 |
|
|
Mar 31 12:25:36 PM PDT 24 |
Mar 31 12:25:37 PM PDT 24 |
90231178 ps |
| T1007 |
/workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.1408825571 |
|
|
Mar 31 12:25:17 PM PDT 24 |
Mar 31 12:25:18 PM PDT 24 |
20725801 ps |
| T1008 |
/workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.241118215 |
|
|
Mar 31 12:25:12 PM PDT 24 |
Mar 31 12:25:13 PM PDT 24 |
35978616 ps |
| T1009 |
/workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.139961921 |
|
|
Mar 31 12:25:35 PM PDT 24 |
Mar 31 12:25:36 PM PDT 24 |
22717259 ps |
| T1010 |
/workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.3892913750 |
|
|
Mar 31 12:25:13 PM PDT 24 |
Mar 31 12:25:13 PM PDT 24 |
26725503 ps |
| T1011 |
/workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.250427868 |
|
|
Mar 31 12:26:42 PM PDT 24 |
Mar 31 12:26:43 PM PDT 24 |
239586749 ps |
| T1012 |
/workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.2563703340 |
|
|
Mar 31 12:25:10 PM PDT 24 |
Mar 31 12:25:10 PM PDT 24 |
38741828 ps |
| T1013 |
/workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.605237839 |
|
|
Mar 31 12:25:26 PM PDT 24 |
Mar 31 12:25:26 PM PDT 24 |
19978357 ps |
| T1014 |
/workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.334346233 |
|
|
Mar 31 12:25:14 PM PDT 24 |
Mar 31 12:25:15 PM PDT 24 |
21345407 ps |
| T1015 |
/workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.717763459 |
|
|
Mar 31 12:25:48 PM PDT 24 |
Mar 31 12:25:48 PM PDT 24 |
83730515 ps |
| T1016 |
/workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3110071129 |
|
|
Mar 31 12:25:23 PM PDT 24 |
Mar 31 12:25:23 PM PDT 24 |
18397163 ps |