Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	467073	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

176608

1

T1

14

T2

75

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	333814	1			T1	39		T2	165		T3	47
values[0x0]	154953	1			T1	11		T2	84		T3	15
values[0x1]	154914	1			T1	11		T2	98		T3	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	370060	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

273621

1

T1

27

T2

121

T3

28

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2252	1			T7	31		T14	54		T25	4
valid_sources[0x01]	2594	1			T2	3		T4	1		T7	49
valid_sources[0x02]	2845	1			T2	3		T4	4		T7	39
valid_sources[0x03]	3046	1			T5	1		T6	5		T7	49
valid_sources[0x04]	2280	1			T1	1		T4	1		T5	1
valid_sources[0x05]	1961	1			T2	2		T7	40		T9	24
valid_sources[0x06]	1974	1			T7	34		T14	43		T26	3
valid_sources[0x07]	1990	1			T7	48		T14	49		T74	6
valid_sources[0x08]	2399	1			T7	60		T14	36		T26	3
valid_sources[0x09]	2632	1			T4	3		T7	41		T14	45
valid_sources[0x0a]	2112	1			T7	34		T14	45		T22	1
valid_sources[0x0b]	1942	1			T4	6		T7	39		T14	41
valid_sources[0x0c]	2106	1			T6	6		T7	44		T14	38
valid_sources[0x0d]	2237	1			T1	1		T2	1		T7	39
valid_sources[0x0e]	2101	1			T1	1		T2	4		T7	45
valid_sources[0x0f]	3027	1			T2	2		T7	81		T14	44
valid_sources[0x10]	3733	1			T7	42		T10	1		T14	45
valid_sources[0x11]	2753	1			T3	1		T7	39		T14	40
valid_sources[0x12]	2003	1			T1	1		T7	54		T14	39
valid_sources[0x13]	2818	1			T2	1		T7	41		T14	40
valid_sources[0x14]	2350	1			T7	37		T14	34		T26	2
valid_sources[0x15]	2091	1			T7	48		T14	50		T26	2
valid_sources[0x16]	3279	1			T7	55		T14	57		T26	2
valid_sources[0x17]	2004	1			T7	44		T14	42		T27	1
valid_sources[0x18]	2103	1			T7	53		T9	14		T10	3
valid_sources[0x19]	2376	1			T2	4		T4	2		T7	57
valid_sources[0x1a]	2499	1			T1	1		T6	15		T7	36
valid_sources[0x1b]	2231	1			T7	57		T10	1		T14	39
valid_sources[0x1c]	2425	1			T2	3		T7	34		T14	36
valid_sources[0x1d]	2054	1			T6	4		T7	44		T14	33
valid_sources[0x1e]	2120	1			T7	42		T14	55		T25	1
valid_sources[0x1f]	4515	1			T1	3		T2	4		T6	9
valid_sources[0x20]	3530	1			T2	2		T7	45		T14	37
valid_sources[0x21]	2058	1			T7	46		T14	50		T22	3
valid_sources[0x22]	2611	1			T7	62		T9	13		T14	52
valid_sources[0x23]	2155	1			T2	1		T6	5		T7	42
valid_sources[0x24]	2468	1			T6	1		T7	26		T14	48
valid_sources[0x25]	1933	1			T4	1		T7	40		T14	44
valid_sources[0x26]	3618	1			T2	3		T7	39		T14	41
valid_sources[0x27]	2269	1			T7	54		T14	46		T22	1
valid_sources[0x28]	3116	1			T2	1		T6	1		T7	41
valid_sources[0x29]	2042	1			T6	3		T7	64		T14	43
valid_sources[0x2a]	2320	1			T2	1		T6	3		T7	37
valid_sources[0x2b]	2145	1			T2	1		T7	38		T14	37
valid_sources[0x2c]	2149	1			T7	46		T14	43		T25	1
valid_sources[0x2d]	2034	1			T7	48		T10	1		T14	43
valid_sources[0x2e]	1879	1			T7	49		T14	54		T26	1
valid_sources[0x2f]	2145	1			T2	3		T7	42		T14	45
valid_sources[0x30]	2426	1			T5	1		T7	53		T14	44
valid_sources[0x31]	2981	1			T2	2		T7	45		T9	14
valid_sources[0x32]	2011	1			T2	2		T5	1		T6	1
valid_sources[0x33]	4705	1			T2	2		T6	3		T7	49
valid_sources[0x34]	3598	1			T7	51		T14	29		T22	1
valid_sources[0x35]	2155	1			T2	3		T6	11		T7	29
valid_sources[0x36]	2279	1			T1	2		T2	9		T5	1
valid_sources[0x37]	2056	1			T6	3		T7	42		T9	15
valid_sources[0x38]	2054	1			T4	3		T5	1		T7	53
valid_sources[0x39]	2159	1			T1	2		T4	1		T5	1
valid_sources[0x3a]	2044	1			T2	2		T7	46		T14	40
valid_sources[0x3b]	2131	1			T2	2		T7	36		T9	6
valid_sources[0x3c]	2153	1			T7	47		T14	53		T26	5
valid_sources[0x3d]	2147	1			T2	3		T6	7		T7	38
valid_sources[0x3e]	2839	1			T7	37		T14	49		T22	1
valid_sources[0x3f]	2224	1			T7	53		T14	38		T25	1
valid_sources[0x40]	2746	1			T7	53		T14	52		T22	1
valid_sources[0x41]	3276	1			T2	2		T3	3		T7	47
valid_sources[0x42]	3978	1			T6	3		T7	64		T14	34
valid_sources[0x43]	2303	1			T2	1		T4	4		T7	43
valid_sources[0x44]	2220	1			T4	3		T6	2		T7	34
valid_sources[0x45]	3041	1			T1	2		T7	66		T14	36
valid_sources[0x46]	2913	1			T2	4		T7	42		T33	1
valid_sources[0x47]	2334	1			T2	1		T7	39		T14	39
valid_sources[0x48]	1944	1			T5	2		T6	2		T7	37
valid_sources[0x49]	2281	1			T5	1		T6	3		T7	27
valid_sources[0x4a]	2897	1			T7	60		T14	45		T26	3
valid_sources[0x4b]	2653	1			T2	2		T7	69		T14	31
valid_sources[0x4c]	3014	1			T6	2		T7	46		T14	56
valid_sources[0x4d]	2264	1			T2	2		T7	34		T14	39
valid_sources[0x4e]	2178	1			T6	2		T7	35		T14	36
valid_sources[0x4f]	3021	1			T7	51		T9	14		T14	49
valid_sources[0x50]	2061	1			T7	49		T14	50		T25	1
valid_sources[0x51]	2391	1			T2	3		T7	45		T14	47
valid_sources[0x52]	3686	1			T2	1		T7	36		T14	38
valid_sources[0x53]	2344	1			T2	3		T6	4		T7	47
valid_sources[0x54]	2593	1			T2	3		T7	39		T8	1
valid_sources[0x55]	2456	1			T2	6		T7	33		T14	45
valid_sources[0x56]	2932	1			T7	55		T14	51		T25	1
valid_sources[0x57]	1938	1			T7	50		T14	37		T26	2
valid_sources[0x58]	2277	1			T1	1		T2	1		T7	50
valid_sources[0x59]	4946	1			T2	5		T7	36		T14	44
valid_sources[0x5a]	3032	1			T2	2		T4	3		T7	33
valid_sources[0x5b]	2122	1			T1	3		T2	1		T7	42
valid_sources[0x5c]	2205	1			T6	4		T7	47		T10	1
valid_sources[0x5d]	2406	1			T4	2		T7	67		T9	15
valid_sources[0x5e]	2324	1			T2	1		T6	1		T7	33
valid_sources[0x5f]	3012	1			T2	3		T3	4		T7	37
valid_sources[0x60]	2095	1			T2	5		T6	4		T7	46
valid_sources[0x61]	2979	1			T1	1		T6	1		T7	38
valid_sources[0x62]	2254	1			T2	2		T7	48		T14	47
valid_sources[0x63]	2118	1			T2	3		T6	9		T7	54
valid_sources[0x64]	2130	1			T2	1		T6	4		T7	42
valid_sources[0x65]	2490	1			T7	49		T14	40		T26	1
valid_sources[0x66]	2146	1			T1	2		T2	1		T7	32
valid_sources[0x67]	2463	1			T1	1		T2	1		T3	6
valid_sources[0x68]	3350	1			T2	9		T7	44		T14	46
valid_sources[0x69]	2191	1			T5	1		T7	40		T14	44
valid_sources[0x6a]	2038	1			T7	42		T14	30		T78	5
valid_sources[0x6b]	2162	1			T2	11		T7	50		T14	44
valid_sources[0x6c]	1959	1			T7	50		T9	27		T14	40
valid_sources[0x6d]	2116	1			T2	9		T7	29		T14	52
valid_sources[0x6e]	2188	1			T7	38		T14	51		T22	1
valid_sources[0x6f]	2392	1			T1	1		T5	2		T7	56
valid_sources[0x70]	2103	1			T2	2		T5	1		T7	61
valid_sources[0x71]	2441	1			T2	3		T7	50		T14	36
valid_sources[0x72]	2893	1			T2	1		T7	58		T14	47
valid_sources[0x73]	2162	1			T2	2		T7	26		T14	45
valid_sources[0x74]	2029	1			T2	5		T6	10		T7	58
valid_sources[0x75]	2301	1			T2	2		T6	1		T7	41
valid_sources[0x76]	2174	1			T7	59		T14	47		T25	1
valid_sources[0x77]	2044	1			T2	4		T7	28		T14	45
valid_sources[0x78]	2822	1			T5	1		T7	59		T14	38
valid_sources[0x79]	1902	1			T6	7		T7	51		T14	47
valid_sources[0x7a]	2137	1			T2	3		T3	1		T5	1
valid_sources[0x7b]	2147	1			T2	1		T7	42		T14	50
valid_sources[0x7c]	1946	1			T2	6		T7	49		T14	50
valid_sources[0x7d]	2991	1			T7	53		T14	44		T22	1
valid_sources[0x7e]	1914	1			T3	1		T7	41		T14	46
valid_sources[0x7f]	2400	1			T7	28		T14	41		T22	2
valid_sources[0x80]	2129	1			T5	2		T7	57		T14	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87625

1

T1

7

T2

28

T3

9

values[0x0]

all_enables

biggest_size

58015

1

T1

5

T2

31

T3

1

values[0x1]

all_enables

biggest_size

30968

1

T1

2

T2

16

T3

1