SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34690 | 1 | T7 | 1 | T26 | 404 | T77 | 286 | ||||
others[1] | 34796 | 1 | T7 | 1 | T22 | 1 | T26 | 427 | ||||
others[2] | 34767 | 1 | T1 | 1 | T22 | 1 | T26 | 397 | ||||
others[3] | 57889 | 1 | T7 | 2 | T22 | 1 | T26 | 630 | ||||
false | 17607 | 1 | T1 | 3 | T2 | 40 | T7 | 340 | ||||
true | 27203 | 1 | T1 | 5 | T2 | 42 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34718 | 1 | T7 | 1 | T26 | 385 | T29 | 1 | ||||
others[1] | 34673 | 1 | T22 | 1 | T25 | 1 | T26 | 418 | ||||
others[2] | 34983 | 1 | T7 | 1 | T25 | 1 | T26 | 397 | ||||
others[3] | 57736 | 1 | T1 | 1 | T25 | 1 | T26 | 669 | ||||
false | 11381 | 1 | T1 | 4 | T2 | 20 | T7 | 173 | ||||
true | 21033 | 1 | T1 | 6 | T2 | 22 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 681 | 1 | T3 | 1 | T7 | 11 | T14 | 7 | ||||
others[1] | 669 | 1 | T3 | 1 | T6 | 1 | T7 | 10 | ||||
others[2] | 634 | 1 | T1 | 1 | T7 | 7 | T10 | 1 | ||||
others[3] | 1084 | 1 | T4 | 1 | T7 | 15 | T10 | 1 | ||||
false | 12793 | 1 | T1 | 5 | T2 | 2 | T3 | 6 | ||||
true | 3771 | 1 | T1 | 3 | T3 | 3 | T4 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |